PUNPCKHQDQ instruction (SSE2)

PUNPCKHQDQ takes the high quadword of its source and writes it above the high quadword of its destination: the result is the destination’s bits 127:64 followed by the source’s bits 127:64, and both low halves are dropped. On Zen 5, punpckhqdq xmm7, xmmword ptr [mem] moved the destination’s own bits 127:64 (4E4134271A0D00F3h) down to bits 63:0 and wrote the memory operand’s bits 127:64 (3AFFC4894E13D89Dh) into bits 127:64, leaving the low eight bytes of the 16-byte memory operand unused and bits 511:128 of ZMM7 as they were. Like PUNPCKLQDQ, which joins the low halves, it has no MMX form and came only with SSE2.

Moving the high half down

The usual job is a horizontal reduction: summing the two 64-bit lanes of a vector needs the high one brought down first. For _mm_cvtsi128_si64(_mm_add_epi64(v, _mm_unpackhi_epi64(v, v))), GCC 14 at -O2 copies v, unpacks its high quadword into both halves of another register with PUNPCKHQDQ and adds the copy to it; Clang 23 instead moves the high doubleword pair down with PSHUFD and EEh, never using this pack for the job, at the default target and at -march=x86-64-v2 alike.

The floating twin is UNPCKHPD. For double t[2]; _mm_storeu_pd(t, v); return t[1];, which reads the high double back out of a store, GCC 14 at -O2 compiles the extraction to UNPCKHPD and Clang 23 to MOVHLPS, at the default target and at -march=x86-64-v2 alike.

AMD’s latency spreadsheet for Zen 5 gives PUNPCKHQDQ one macro-op with a latency of one cycle, four per cycle. VPUNPCKHQDQ, the VEX and EVEX form, unpacks each 128-bit lane on its own, as VPUNPCKLQDQ shows.

Forms

Every encoding of PUNPCKHQDQ that Intel XED knows, one row per XED instruction form (iform). How to read the notation.

Instruction	Encoding	Requires
`PUNPCKHQDQ xmm, m128` PUNPCKHQDQ_XMMdq_MEMdq	`66 0F 6D /r`	SSE2
`PUNPCKHQDQ xmm, xmm` PUNPCKHQDQ_XMMdq_XMMq	`66 0F 6D /r`	SSE2

Data flow

Where the elements of the sources go, element 0 on the right; results that depend on a control value are drawn for an example. How to read.

Interleave: the high quadwords of both sources alternate in the result, those of xmm1 in the even places.

Result quadwords 1 to 0: b1, a1.

Operation

What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.

src1 = xmm1.read()  # xmm1 as it was
for i in range(2):
    j = i // 2 + 1
    if i % 2 == 0:
        xmm1.q[i] = src1.q[j]
    else:
        xmm1.q[i] = src2.q[j]
# bits 128 and up of the register are unchanged

Run on AMD Zen 5 (EPYC 9645): 2 cases.

Operands

What each form reads and writes, as Intel XED records it: the operands of its syntax, in order, and the implicit ones that the syntax does not name. How to read.

Operand	Kind	Action
`PUNPCKHQDQ xmm, xmm/m128`
`xmm`	explicit	read, write
`xmm/m128`	explicit	read

Flags

None: XED records no flag that the forms test or change.

Exceptions

The exception class is XED's name for the set of exception conditions that a form follows. How to read.

All forms: SSE_TYPE_4

Attributes

What else XED records about the forms. How to read.

Memory forms: aligned memory operand

Intrinsics

The C intrinsics of Clang 23.1.2 that compile to PUNPCKHQDQ, each with the form it compiles to and the Clang options it needs. The forms come from compiling every intrinsic and decoding the result with Intel XED; all intrinsics A–Z explains the method.

Intrinsic	Compiles to
`_mm_unpackhi_epi64` `__m128i _mm_unpackhi_epi64(__m128i __a, __m128i __b)`	`PUNPCKHQDQ xmm, xmm` Legacy -msse2

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

CPUID requirements and processors of the XED ISA sets above. Alternatives are separated by “or”; processors follow XED’s chip model, whose AMD processors end with Zen 2, and the CPU data of this site for Zen 3 to Zen 6.

ISA set	CPUID	Processors
`SSE2` SSE2	SSE2 `CPUID.01H:EDX[26]` SSE2	Every x86-64 processor in XED’s model and Zen 3 to Zen 6

More SSE2 instructions

All 124 SSE2 instructions

Moving the high half down#