PUNPCKHWD instruction (MMX, SSE2)

PUNPCKHWD takes the high half of each operand and interleaves the two word by word: word 4 of the destination, word 4 of the source, word 5 of each, and so on, until the four high words of each (two in the MMX form) fill the register. On Zen 5, punpckhwd xmm7, xmm11 turned words 4 to 7 of XMM7, 00F3h, 1A0Dh, 3427h and 4E41h, and those of XMM11, 1C0Fh, 3629h, 5043h and 6A5Dh, into 00F3h, 1C0Fh, 1A0Dh, 3629h and so on, and kept bits 511:128 of ZMM7. PUNPCKLBW describes the unpacks and their pairings; PUNPCKLWD takes the low halves.

Words to doublewords

Each pairing turns four words into four doublewords:

With a zeroed register, the high words zero-extended. Intel’s optimization manual widens eight words this way, PUNPCKLWD for the low four and PUNPCKHWD for the high four (Section 6.4.1), and GCC 14 at -O2 does the same for uint16_t to uint32_t in our builds for the SSE2 baseline. Clang 23 loads eight bytes at a time and needs only the low unpack. With -march=x86-64-v2 both use PMOVZXWD.
With itself, each word in the high half of a doubleword, where an arithmetic shift right by 16 (PSRAD) sign-extends it (Section 6.4.2).
With the high halves of products. For d[i] = a[i] * b[i] with int16_t sources and an int32_t result, GCC computes the low and high 16 bits of each product with PMULLW and PMULHW and joins them with PUNPCKLWD and PUNPCKHWD, also at x86-64-v2. Clang instead spreads the factors over doublewords and multiplies with PMADDWD.

Interleaving two arrays of int16_t, c[2*i] = a[i]; c[2*i+1] = b[i], is a low and a high unpack of the same two registers in GCC; Clang again loads eight bytes and uses the low one. GCC’s baseline code for truncating uint32_t values to uint16_t is also built from unpacks, five per eight results.

In the MMX form a memory operand is eight bytes; in the SSE2 form it is 16 bytes aligned to 16. AMD’s latency spreadsheet for Zen 5 gives PUNPCKHWD a latency of one cycle, four per cycle. VPUNPCKHWD, the VEX and EVEX form, unpacks each 128-bit lane on its own, as VPUNPCKHBW shows.

Forms

Every encoding of PUNPCKHWD that Intel XED knows, one row per XED instruction form (iform). How to read the notation.

Instruction	Encoding	Requires
`PUNPCKHWD mm, m64` PUNPCKHWD_MMXq_MEMq	`NP 0F 69 /r`	MMX
`PUNPCKHWD mm, mm` PUNPCKHWD_MMXq_MMXd	`NP 0F 69 /r`	MMX
`PUNPCKHWD xmm, m128` PUNPCKHWD_XMMdq_MEMdq	`66 0F 69 /r`	SSE2
`PUNPCKHWD xmm, xmm` PUNPCKHWD_XMMdq_XMMq	`66 0F 69 /r`	SSE2

Data flow

Where the elements of the sources go, element 0 on the right; results that depend on a control value are drawn for an example. How to read.

Interleave: the high words of both sources alternate in the result, those of xmm1 in the even places.

Result words 7 to 0: b7, a7, b6, a6, b5, a5, b4, a4.

Operation

What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.

PUNPCKHWD mm, mm/m64

src1 = mm1.read()  # mm1 as it was
for i in range(4):
    j = i // 2 + 2
    if i % 2 == 0:
        mm1.w[i] = src1.w[j]
    else:
        mm1.w[i] = src2.w[j]
# x87: TOP = 0, all tags valid, bits 79:64 of mm1's register all ones

Run on AMD Zen 5 (EPYC 9645): 2 cases.

PUNPCKHWD xmm, xmm/m128

src1 = xmm1.read()  # xmm1 as it was
for i in range(8):
    j = i // 2 + 4
    if i % 2 == 0:
        xmm1.w[i] = src1.w[j]
    else:
        xmm1.w[i] = src2.w[j]
# bits 128 and up of the register are unchanged

Run on AMD Zen 5 (EPYC 9645): 2 cases.

Operands

What each form reads and writes, as Intel XED records it: the operands of its syntax, in order, and the implicit ones that the syntax does not name. How to read.

Operand	Kind	Action
`PUNPCKHWD mm, mm/m64`
`mm`	explicit	read, write
`mm/m64`	explicit	read
`PUNPCKHWD xmm, xmm/m128`
`xmm`	explicit	read, write
`xmm/m128`	explicit	read

Flags

None: XED records no flag that the forms test or change.

Exceptions

The exception class is XED's name for the set of exception conditions that a form follows. How to read.

PUNPCKHWD mm, mm/m64: mmx-mem
PUNPCKHWD xmm, xmm/m128: SSE_TYPE_4

Attributes

What else XED records about the forms. How to read.

PUNPCKHWD mm, mm/m64: may abort a TSX transaction
PUNPCKHWD xmm, m128: aligned memory operand

Intrinsics

The C intrinsics of Clang 23.1.2 that compile to PUNPCKHWD, each with the form it compiles to and the Clang options it needs. The forms come from compiling every intrinsic and decoding the result with Intel XED; all intrinsics A–Z explains the method.

Intrinsic	Compiles to
`_mm_unpackhi_epi16` `__m128i _mm_unpackhi_epi16(__m128i __a, __m128i __b)`	`PUNPCKHWD xmm, xmm` Legacy -msse2

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

CPUID requirements and processors of the XED ISA sets above. Alternatives are separated by “or”; processors follow XED’s chip model, whose AMD processors end with Zen 2, and the CPU data of this site for Zen 3 to Zen 6.

ISA set	CPUID	Processors
`PENTIUMMMX` MMX	MMX `CPUID.01H:EDX[23]` MMX	Every x86-64 processor in XED’s model and Zen 3 to Zen 6
`SSE2` SSE2	SSE2 `CPUID.01H:EDX[26]` SSE2	Every x86-64 processor in XED’s model and Zen 3 to Zen 6

More MMX instructions

All 47 MMX instructions

More SSE2 instructions

All 124 SSE2 instructions

Words to doublewords#