PUNPCKLBW instruction (MMX, SSE2)

PUNPCKLBW takes the low half of each operand and interleaves the two byte by byte: byte 0 of the destination, byte 0 of the source, byte 1 of the destination, byte 1 of the source, and so on, until the eight low bytes of each (four in the MMX form) fill the register. The high halves are ignored; PUNPCKHBW does the same with them. In the intrinsic _mm_unpacklo_epi8(a, b), the bytes of a land in the even positions.

What makes it common is the operand it is paired with:

A zeroed register turns eight bytes into eight words, zero-extended. Compiling for the SSE2 baseline, GCC 14 and Clang 23 at -O2 widen uint8_t elements to uint16_t this way: GCC loads 16 bytes and splits them with PUNPCKLBW and PUNPCKHBW against a PXOR-zeroed register, Clang loads eight bytes at a time with MOVQ and uses PUNPCKLBW alone. With -msse4.1 both use PMOVZXBW instead.
A register of sign bytes sign-extends. For int8_t to int16_t, GCC builds FFh for each negative byte with PCMPGTB of zero against the data and interleaves that; Clang interleaves the data with itself, which puts each byte in both halves of a word, and shifts the words right arithmetically by 8 with PSRAW.
The same register doubles every byte, the first step of a byte broadcast. For _mm_set1_epi8(c) without SSSE3, GCC emits MOVD, PUNPCKLBW, PUNPCKLWD and PSHUFD with 00h; Clang replaces the second unpack with PSHUFLW.

Widened data usually comes back to bytes with PACKUSWB after the arithmetic.

In the MMX form a memory operand is 32 bits, just the four bytes used. In the SSE2 form it is 16 bytes and must be aligned to 16, even though only the low eight count; Intel’s manual lets a processor fetch only those eight, but still checks the alignment. VPUNPCKLBW, the VEX and EVEX form, interleaves the low halves of each 128-bit lane separately, so a 256-bit result holds source bytes 0 to 7 and 16 to 23, not 0 to 15. PUNPCKLWD, PUNPCKLDQ and PUNPCKLQDQ interleave larger elements.

Forms

Every encoding of PUNPCKLBW that Intel XED knows, one row per XED instruction form (iform). How to read the notation.

Instruction	Encoding	Requires
`PUNPCKLBW mm, m32` PUNPCKLBW_MMXq_MEMd	`NP 0F 60 /r`	MMX
`PUNPCKLBW mm, mm` PUNPCKLBW_MMXq_MMXd	`NP 0F 60 /r`	MMX
`PUNPCKLBW xmm, m128` PUNPCKLBW_XMMdq_MEMdq	`66 0F 60 /r`	SSE2
`PUNPCKLBW xmm, xmm` PUNPCKLBW_XMMdq_XMMq	`66 0F 60 /r`	SSE2

Data flow

Where the elements of the sources go, element 0 on the right; results that depend on a control value are drawn for an example. How to read.

Interleave: the low bytes of both sources alternate in the result, those of xmm1 in the even places.

Result bytes 15 to 0: b7, a7, b6, a6, b5, a5, b4, a4, b3, a3, b2, a2, b1, a1, b0, a0.

Operation

What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.

PUNPCKLBW mm, mm/m32

src1 = mm1.read()  # mm1 as it was
for i in range(8):
    j = i // 2
    if i % 2 == 0:
        mm1.b[i] = src1.b[j]
    else:
        mm1.b[i] = src2.b[j]
# x87: TOP = 0, all tags valid, bits 79:64 of mm1's register all ones

Run on AMD Zen 5 (EPYC 9645): 2 cases.

PUNPCKLBW xmm, xmm/m128

src1 = xmm1.read()  # xmm1 as it was
for i in range(16):
    j = i // 2
    if i % 2 == 0:
        xmm1.b[i] = src1.b[j]
    else:
        xmm1.b[i] = src2.b[j]
# bits 128 and up of the register are unchanged

Run on AMD Zen 5 (EPYC 9645): 2 cases.

Operands

What each form reads and writes, as Intel XED records it: the operands of its syntax, in order, and the implicit ones that the syntax does not name. How to read.

Operand	Kind	Action
`PUNPCKLBW mm, mm/m32`
`mm`	explicit	read, write
`mm/m32`	explicit	read
`PUNPCKLBW xmm, xmm/m128`
`xmm`	explicit	read, write
`xmm/m128`	explicit	read

Flags

None: XED records no flag that the forms test or change.

Exceptions

The exception class is XED's name for the set of exception conditions that a form follows. How to read.

PUNPCKLBW mm, mm/m32: mmx-mem
PUNPCKLBW xmm, xmm/m128: SSE_TYPE_4

Attributes

What else XED records about the forms. How to read.

PUNPCKLBW mm, mm/m32: may abort a TSX transaction
PUNPCKLBW xmm, m128: aligned memory operand

Intrinsics

The C intrinsics of Clang 23.1.2 that compile to PUNPCKLBW, each with the form it compiles to and the Clang options it needs. The forms come from compiling every intrinsic and decoding the result with Intel XED; all intrinsics A–Z explains the method.

Intrinsic	Compiles to
`_mm_unpacklo_epi8` `__m128i _mm_unpacklo_epi8(__m128i __a, __m128i __b)`	`PUNPCKLBW xmm, xmm` Legacy -msse2
`_mm_unpacklo_pi8` `__m64 _mm_unpacklo_pi8(__m64 __m1, __m64 __m2)`	`PUNPCKLBW xmm, xmm` Legacy -msse2

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

CPUID requirements and processors of the XED ISA sets above. Alternatives are separated by “or”; processors follow XED’s chip model, whose AMD processors end with Zen 2, and the CPU data of this site for Zen 3 to Zen 6.

ISA set	CPUID	Processors
`PENTIUMMMX` MMX	MMX `CPUID.01H:EDX[23]` MMX	Every x86-64 processor in XED’s model and Zen 3 to Zen 6
`SSE2` SSE2	SSE2 `CPUID.01H:EDX[26]` SSE2	Every x86-64 processor in XED’s model and Zen 3 to Zen 6

More MMX instructions

All 47 MMX instructions

More SSE2 instructions

All 124 SSE2 instructions