PUNPCKLDQ instruction (MMX, SSE2)

PUNPCKLDQ interleaves the low doublewords of its two operands: doubleword 0 of the destination, doubleword 0 of the source, then doubleword 1 of each. On Zen 5, punpckldq xmm4, xmmword ptr [mem] gave 9D908376h, 763B00C5h, D1C4B7AAh and 6227ECB1h, the first and third from XMM4 and the others from memory, and kept bits 511:128 of ZMM4. The MMX form reads only four bytes from memory, as punpckldq mm7, dword ptr [mem] did; the SSE2 form takes 16 bytes aligned to 16, of which only the low eight count. PUNPCKLBW describes the family and its pairings, and PUNPCKHDQ takes the high halves.

Glue for doublewords

Compilers use it wherever two 32-bit values become one 64-bit half. In our builds at -O2 for the SSE2 baseline, GCC 14 and Clang 23:

build _mm_setr_epi32(a, b, c, d) from four MOVDs, two PUNPCKLDQs for the pairs and one PUNPCKLQDQ to join them. With -march=x86-64-v2 both insert with PINSRD instead, GCC the second element of each pair, Clang all three after the first;
zero-extend uint32_t to uint64_t by interleaving with a zeroed register, the job of PMOVZXDQ since SSE4.1;
sign-extend int32_t to int64_t by interleaving with the sign masks that PCMPGTD computes, the job of PMOVSXDQ.

Interleaving two int arrays, c[2*i] = a[i]; c[2*i+1] = b[i], is a PUNPCKLDQ and a PUNPCKHDQ of the same two registers in GCC. Clang writes UNPCKLPS for it, the single-precision twin, which moves the same bits: LLVM picks between the integer and floating-point forms of a shuffle by the instructions around it, so the same C can give either. For a 4x4 transpose of integer vectors written with _mm_unpacklo_epi32 and its kin, GCC keeps the integer unpacks while Clang turns all eight into UNPCKLPS, UNPCKHPS, MOVLHPS and UNPCKHPD.

AMD’s latency spreadsheet for Zen 5 gives PUNPCKLDQ one macro-op with a latency of one cycle, four per cycle. VPUNPCKLDQ is the VEX and EVEX form, which interleaves within each 128-bit lane.

Forms

Every encoding of PUNPCKLDQ that Intel XED knows, one row per XED instruction form (iform). How to read the notation.

Instruction	Encoding	Requires
`PUNPCKLDQ mm, m32` PUNPCKLDQ_MMXq_MEMd	`NP 0F 62 /r`	MMX
`PUNPCKLDQ mm, mm` PUNPCKLDQ_MMXq_MMXd	`NP 0F 62 /r`	MMX
`PUNPCKLDQ xmm, m128` PUNPCKLDQ_XMMdq_MEMdq	`66 0F 62 /r`	SSE2
`PUNPCKLDQ xmm, xmm` PUNPCKLDQ_XMMdq_XMMq	`66 0F 62 /r`	SSE2

Data flow

Where the elements of the sources go, element 0 on the right; results that depend on a control value are drawn for an example. How to read.

Interleave: the low doublewords of both sources alternate in the result, those of xmm1 in the even places.

Result doublewords 3 to 0: b1, a1, b0, a0.

Operation

What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.

PUNPCKLDQ mm, mm/m32

src1 = mm1.read()  # mm1 as it was
for i in range(2):
    j = i // 2
    if i % 2 == 0:
        mm1.d[i] = src1.d[j]
    else:
        mm1.d[i] = src2.d[j]
# x87: TOP = 0, all tags valid, bits 79:64 of mm1's register all ones

Run on AMD Zen 5 (EPYC 9645): 2 cases.

PUNPCKLDQ xmm, xmm/m128

src1 = xmm1.read()  # xmm1 as it was
for i in range(4):
    j = i // 2
    if i % 2 == 0:
        xmm1.d[i] = src1.d[j]
    else:
        xmm1.d[i] = src2.d[j]
# bits 128 and up of the register are unchanged

Run on AMD Zen 5 (EPYC 9645): 2 cases.

Operands

What each form reads and writes, as Intel XED records it: the operands of its syntax, in order, and the implicit ones that the syntax does not name. How to read.

Operand	Kind	Action
`PUNPCKLDQ mm, mm/m32`
`mm`	explicit	read, write
`mm/m32`	explicit	read
`PUNPCKLDQ xmm, xmm/m128`
`xmm`	explicit	read, write
`xmm/m128`	explicit	read

Flags

None: XED records no flag that the forms test or change.

Exceptions

The exception class is XED's name for the set of exception conditions that a form follows. How to read.

PUNPCKLDQ mm, mm/m32: none in XED
PUNPCKLDQ xmm, xmm/m128: SSE_TYPE_4

Attributes

What else XED records about the forms. How to read.

PUNPCKLDQ mm, mm/m32: may abort a TSX transaction
PUNPCKLDQ xmm, m128: aligned memory operand

Intrinsics

The C intrinsics of Clang 23.1.2 that compile to PUNPCKLDQ, each with the form it compiles to and the Clang options it needs. The forms come from compiling every intrinsic and decoding the result with Intel XED; all intrinsics A–Z explains the method.

Intrinsic	Compiles to
`_mm_unpacklo_epi32` `__m128i _mm_unpacklo_epi32(__m128i __a, __m128i __b)`	`PUNPCKLDQ xmm, xmm` Legacy -msse2
`_mm_unpacklo_pi32` `__m64 _mm_unpacklo_pi32(__m64 __m1, __m64 __m2)`	`PUNPCKLDQ xmm, xmm` Legacy -msse2

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

CPUID requirements and processors of the XED ISA sets above. Alternatives are separated by “or”; processors follow XED’s chip model, whose AMD processors end with Zen 2, and the CPU data of this site for Zen 3 to Zen 6.

ISA set	CPUID	Processors
`PENTIUMMMX` MMX	MMX `CPUID.01H:EDX[23]` MMX	Every x86-64 processor in XED’s model and Zen 3 to Zen 6
`SSE2` SSE2	SSE2 `CPUID.01H:EDX[26]` SSE2	Every x86-64 processor in XED’s model and Zen 3 to Zen 6

More MMX instructions

All 47 MMX instructions

More SSE2 instructions

All 124 SSE2 instructions

Glue for doublewords#