PUNPCKLQDQ instruction (SSE2)

PUNPCKLQDQ puts the low quadword of its source above the low quadword of its destination: the result is the destination’s bits 63:0 followed by the source’s bits 63:0, and both high halves are dropped. On Zen 5, punpcklqdq xmm1, xmm2 kept bits 63:0 of XMM1, wrote bits 63:0 of XMM2 into bits 127:64, and left bits 511:128 of ZMM1 alone. Unlike the narrower unpacks it has no MMX form, as an MMX register holds only one quadword; it came with SSE2, and a memory operand is 16 bytes aligned to 16, of which only the low eight count. Intel’s optimization manual describes it with its partner PUNPCKHQDQ, which joins the high halves (Section 6.4.14).

Joining halves

With elements this wide, interleaving is just joining two 64-bit halves, and compilers use it as the last step of many sequences. In our builds at -O2 for the SSE2 baseline:

_mm_set_epi64x(b, a) is MOVQ of each value and one PUNPCKLQDQ in both GCC 14 and Clang 23. With -march=x86-64-v2, GCC inserts the second value with PINSRQ instead; Clang keeps the unpack.
_mm_setr_epi32(a, b, c, d) builds two pairs with PUNPCKLDQ and joins them with PUNPCKLQDQ, and GCC’s _mm_setr_epi16 does the same after pairing words with PINSRW.
_mm_set1_epi64x(x), a broadcast, is punpcklqdq xmm0, xmm0 after MOVQ in GCC, and pshufd xmm0, xmm0, 44h in Clang.
Truncating uint32_t values to uint16_t, Clang gathers the low words of each 16-byte load into its low half, with PSHUFLW, PSHUFHW and PSHUFD for the baseline or PSHUFB at x86-64-v2, and joins two such halves with PUNPCKLQDQ.

For interleaving two arrays of int64_t, GCC unpacks the low and high quadwords of each pair of loads; Clang copies with scalar MOVs. The floating-point twins are UNPCKLPD and MOVLHPS, and Clang writes MOVLHPS even in a 4x4 transpose of integer vectors spelled with _mm_unpacklo_epi64, where GCC keeps PUNPCKLQDQ.

AMD’s latency spreadsheet for Zen 5 gives PUNPCKLQDQ one macro-op with a latency of one cycle, four per cycle. VPUNPCKLQDQ, the VEX and EVEX form, joins the low quadwords of each 128-bit lane.

Forms

Every encoding of PUNPCKLQDQ that Intel XED knows, one row per XED instruction form (iform). How to read the notation.

Instruction	Encoding	Requires
`PUNPCKLQDQ xmm, m128` PUNPCKLQDQ_XMMdq_MEMdq	`66 0F 6C /r`	SSE2
`PUNPCKLQDQ xmm, xmm` PUNPCKLQDQ_XMMdq_XMMq	`66 0F 6C /r`	SSE2

Data flow

Where the elements of the sources go, element 0 on the right; results that depend on a control value are drawn for an example. How to read.

Interleave: the low quadwords of both sources alternate in the result, those of xmm1 in the even places.

Result quadwords 1 to 0: b0, a0.

Operation

What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.

src1 = xmm1.read()  # xmm1 as it was
for i in range(2):
    j = i // 2
    if i % 2 == 0:
        xmm1.q[i] = src1.q[j]
    else:
        xmm1.q[i] = src2.q[j]
# bits 128 and up of the register are unchanged

Run on AMD Zen 5 (EPYC 9645): 2 cases.

Operands

What each form reads and writes, as Intel XED records it: the operands of its syntax, in order, and the implicit ones that the syntax does not name. How to read.

Operand	Kind	Action
`PUNPCKLQDQ xmm, xmm/m128`
`xmm`	explicit	read, write
`xmm/m128`	explicit	read

Flags

None: XED records no flag that the forms test or change.

Exceptions

The exception class is XED's name for the set of exception conditions that a form follows. How to read.

All forms: SSE_TYPE_4

Attributes

What else XED records about the forms. How to read.

Memory forms: aligned memory operand

Intrinsics

The C intrinsics of Clang 23.1.2 that compile to PUNPCKLQDQ, each with the form it compiles to and the Clang options it needs. The forms come from compiling every intrinsic and decoding the result with Intel XED; all intrinsics A–Z explains the method.

Intrinsic	Compiles to
`_mm_unpacklo_epi64` `__m128i _mm_unpacklo_epi64(__m128i __a, __m128i __b)`	`PUNPCKLQDQ xmm, xmm` Legacy -msse2

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

CPUID requirements and processors of the XED ISA sets above. Alternatives are separated by “or”; processors follow XED’s chip model, whose AMD processors end with Zen 2, and the CPU data of this site for Zen 3 to Zen 6.

ISA set	CPUID	Processors
`SSE2` SSE2	SSE2 `CPUID.01H:EDX[26]` SSE2	Every x86-64 processor in XED’s model and Zen 3 to Zen 6

More SSE2 instructions

All 124 SSE2 instructions

Joining halves#