PUNPCKLWD instruction (MMX, SSE2)

PUNPCKLWD interleaves the low words of its two operands: word 0 of the destination, word 0 of the source, word 1 of each, and so on, until the four low words of each (two in the MMX form) fill the register. On Zen 5, punpcklwd xmm4, xmmword ptr [mem] gave 8376h, 00C5h, 9D90h, 763Bh, B7AAh, ECB1h, D1C4h and 6227h, the first, third, fifth and seventh from XMM4 and the rest from memory, and kept bits 511:128 of ZMM4. The MMX form reads only a doubleword from memory, two words; the SSE2 form takes 16 bytes aligned to 16, of which only the low eight count. PUNPCKLBW describes the family and its pairings, and PUNPCKHWD, which takes the high halves, covers what compilers build from them: zero- and sign-extending words to doublewords, the two halves of a 16-bit product, and interleaving two arrays of int16_t.

Building a vector of words

PINSRW describes how GCC 14 and Clang 23 build _mm_setr_epi16 at -O2: GCC always pairs words with MOVD and PINSRW, joining the pairs with PUNPCKLDQ and PUNPCKLQDQ. Clang instead pairs the words with this pack for the x86-64 baseline, and only switches to a chain of PINSRWs once SSE4.1 lets it insert each word in place.

AMD’s latency spreadsheet for Zen 5 gives PUNPCKLWD one macro-op with a latency of one cycle, four per cycle. VPUNPCKLWD is the VEX and EVEX form, which interleaves within each 128-bit lane.

Forms

Every encoding of PUNPCKLWD that Intel XED knows, one row per XED instruction form (iform). How to read the notation.

Instruction	Encoding	Requires
`PUNPCKLWD mm, m32` PUNPCKLWD_MMXq_MEMd	`NP 0F 61 /r`	MMX
`PUNPCKLWD mm, mm` PUNPCKLWD_MMXq_MMXd	`NP 0F 61 /r`	MMX
`PUNPCKLWD xmm, m128` PUNPCKLWD_XMMdq_MEMdq	`66 0F 61 /r`	SSE2
`PUNPCKLWD xmm, xmm` PUNPCKLWD_XMMdq_XMMq	`66 0F 61 /r`	SSE2

Data flow

Where the elements of the sources go, element 0 on the right; results that depend on a control value are drawn for an example. How to read.

Interleave: the low words of both sources alternate in the result, those of xmm1 in the even places.

Result words 7 to 0: b3, a3, b2, a2, b1, a1, b0, a0.

Operation

What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.

PUNPCKLWD mm, mm/m32

src1 = mm1.read()  # mm1 as it was
for i in range(4):
    j = i // 2
    if i % 2 == 0:
        mm1.w[i] = src1.w[j]
    else:
        mm1.w[i] = src2.w[j]
# x87: TOP = 0, all tags valid, bits 79:64 of mm1's register all ones

Run on AMD Zen 5 (EPYC 9645): 2 cases.

PUNPCKLWD xmm, xmm/m128

src1 = xmm1.read()  # xmm1 as it was
for i in range(8):
    j = i // 2
    if i % 2 == 0:
        xmm1.w[i] = src1.w[j]
    else:
        xmm1.w[i] = src2.w[j]
# bits 128 and up of the register are unchanged

Run on AMD Zen 5 (EPYC 9645): 2 cases.

Operands

What each form reads and writes, as Intel XED records it: the operands of its syntax, in order, and the implicit ones that the syntax does not name. How to read.

Operand	Kind	Action
`PUNPCKLWD mm, mm/m32`
`mm`	explicit	read, write
`mm/m32`	explicit	read
`PUNPCKLWD xmm, xmm/m128`
`xmm`	explicit	read, write
`xmm/m128`	explicit	read

Flags

None: XED records no flag that the forms test or change.

Exceptions

The exception class is XED's name for the set of exception conditions that a form follows. How to read.

PUNPCKLWD mm, mm/m32: mmx-mem
PUNPCKLWD xmm, xmm/m128: SSE_TYPE_4

Attributes

What else XED records about the forms. How to read.

PUNPCKLWD mm, mm/m32: may abort a TSX transaction
PUNPCKLWD xmm, m128: aligned memory operand

Intrinsics

The C intrinsics of Clang 23.1.2 that compile to PUNPCKLWD, each with the form it compiles to and the Clang options it needs. The forms come from compiling every intrinsic and decoding the result with Intel XED; all intrinsics A–Z explains the method.

Intrinsic	Compiles to
`_mm_unpacklo_epi16` `__m128i _mm_unpacklo_epi16(__m128i __a, __m128i __b)`	`PUNPCKLWD xmm, xmm` Legacy -msse2
`_mm_unpacklo_pi16` `__m64 _mm_unpacklo_pi16(__m64 __m1, __m64 __m2)`	`PUNPCKLWD xmm, xmm` Legacy -msse2

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

CPUID requirements and processors of the XED ISA sets above. Alternatives are separated by “or”; processors follow XED’s chip model, whose AMD processors end with Zen 2, and the CPU data of this site for Zen 3 to Zen 6.

ISA set	CPUID	Processors
`PENTIUMMMX` MMX	MMX `CPUID.01H:EDX[23]` MMX	Every x86-64 processor in XED’s model and Zen 3 to Zen 6
`SSE2` SSE2	SSE2 `CPUID.01H:EDX[26]` SSE2	Every x86-64 processor in XED’s model and Zen 3 to Zen 6

More MMX instructions

All 47 MMX instructions

More SSE2 instructions

All 124 SSE2 instructions

Building a vector of words#