Instruction
PUSH
Moves the stack pointer down and stores a register, memory operand, immediate or segment register on top of the stack.
- Extensions
- Forms
- 11 (11 Legacy)
- Data
- Intel XED v2026.08.23
Forms
| Instruction | Encoding | Requires |
|---|---|---|
PUSH m16/32/64
PUSH_MEMv | FF /6 | Base instruction set |
PUSH r16/32/64
PUSH_GPRv_FFr6 | FF /6 | Base instruction set |
PUSH ES not in 64-bit mode
PUSH_ES | 06 | Base instruction set |
PUSH CS not in 64-bit mode
PUSH_CS | 0E | Base instruction set |
PUSH SS not in 64-bit mode
PUSH_SS | 16 | Base instruction set |
PUSH DS not in 64-bit mode
PUSH_DS | 1E | Base instruction set |
PUSH r16/32/64
PUSH_GPRv_50 | 50+rREX2.W0 50+r | Base instruction set |
PUSH imm16/32
PUSH_IMMz | 68 iw/id | Base instruction set |
PUSH imm8
PUSH_IMMb | 6A ib | Base instruction set |
PUSH FS
PUSH_FS | 0F A0 | Base instruction set |
PUSH GS
PUSH_GS | 0F A8 | Base instruction set |
CPUID and processors
Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.
| ISA set | CPUID | Processors in XED |
|---|---|---|
I86 | No CPUID bit: part of the base instruction set. | Every x86-64 processor in XED’s model |
I186 | No CPUID bit: part of the base instruction set. | Every x86-64 processor in XED’s model |
More General-purpose instructions
Sources
- Intel XED v2026.08.23 (commit
0bcb6237345c): forms, encodings, ISA sets, CPUID bits and chip model. - Intel 64 and IA-32 Architectures Software Developer's Manual, Volume 2 (325383-092, June 2026)
- Intel 64 and IA-32 Architectures Software Developer's Manual, Volume 2 (325383-093, September 2026)
The tables are derived from Intel XED, Copyright Intel Corporation, licensed under the Apache License 2.0; x86-64.net converted and reformatted them. The text is our own.