PUSH2 instruction (APX)

PUSH2 exists because APX doubles the number of general-purpose registers, and with it the registers a function may have to save in its prologue. PUSH2 a, b behaves like PUSH a followed by PUSH b, where a is encoded in the EVEX V field and b in ModRM.rm. Both operands are always 64-bit and neither may be RSP (#UD otherwise), and the two values must land on a 16-byte-aligned stack slot (#GP otherwise). Both values are written or neither is, but the two writes are not guaranteed to be one atomic store.

Paired with POP2 in the epilogue, it halves the number of save and restore instructions. PUSH2P is the same instruction with the push-pop acceleration hint (EVEX.W=1).

Forms

Every encoding of PUSH2 that Intel XED knows, one row per XED instruction form (iform). How to read the notation.

Instruction	Encoding	Requires
`PUSH2 r64, r64` PUSH2_GPR64u64_GPR64u64_APX_N3	`EVEX.LLZ.NP.MAP4.W0 FF /6 ND=1`	APX_F + APX_NCI_NDD_NF

Operation

What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.

if src1.number == 4 or src2.number == 4:
    fault(UD)                    # neither may be RSP
a = rsp - 16
if a % 16 != 0:
    fault(GP, 0)                 # the 16 bytes must be 16-byte aligned
store(a + 8, 64, src1)           # as PUSH src1, then PUSH src2
store(a, 64, src2)
rsp = a

Not run on a processor: none of these processors has APX.

Operands

What each form reads and writes, as Intel XED records it: the operands of its syntax, in order, and the implicit ones that the syntax does not name. How to read.

Operand	Kind	Action
`PUSH2 r64, r64`
`r64`	explicit	read
`r64`	explicit	read
`stack`	implicit	write
`rSP`	implicit	read, write

Flags

None: XED records no flag that the forms test or change.

Exceptions

The exception class is XED's name for the set of exception conditions that a form follows. How to read.

All forms: APX-EVEX-PP2

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

CPUID requirements and processors of the XED ISA sets above. Alternatives are separated by “or”; processors follow XED’s chip model, whose AMD processors end with Zen 2, and the CPU data of this site for Zen 3 to Zen 6.

ISA set	CPUID	Processors
`APX_F_N3` APX	APX_F + APX_NCI_NDD_NF `CPUID.(EAX=07H,ECX=1):EDX[21]` APX_F `CPUID.(EAX=29H,ECX=0):EBX[0]` APX_NCI_NDD_NF	Nova Lake, Diamond Rapids

More APX instructions

All 88 APX instructions