x86-64.net

Instruction

PUSH2

APX instruction that pushes two 64-bit registers to a 16-byte-aligned stack slot.

Extensions
Forms
1 (1 EVEX)
Data
Intel XED v2026.08.23

PUSH2 exists because APX doubles the number of general-purpose registers, and with it the registers a function may have to save in its prologue. PUSH2 a, b behaves like PUSH a followed by PUSH b, where a is encoded in the EVEX V field and b in ModRM.rm. Both operands are always 64-bit and neither may be RSP (#UD otherwise), and the two values must land on a 16-byte-aligned stack slot (#GP otherwise). Both values are written or neither is, but the two writes are not guaranteed to be one atomic store.

Paired with POP2 in the epilogue, it halves the number of save and restore instructions. PUSH2P is the same instruction with the push-pop acceleration hint (EVEX.W=1).

Forms

Every encoding of PUSH2 that Intel XED knows, one row per XED instruction form (iform). How to read the notation.
InstructionEncodingRequires
PUSH2 r64, r64 PUSH2_GPR64u64_GPR64u64_APX_N3EVEX.LLZ.NP.MAP4.W0 FF /6 ND=1APX_F + APX_NCI_NDD_NF

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

CPUID requirements and processors of the XED ISA sets above. Alternatives are separated by “or”; processors follow XED’s chip model, which covers AMD processors up to Zen 2.
ISA setCPUIDProcessors in XED
APX_F_N3

APX_F + APX_NCI_NDD_NF
CPUID.(EAX=07H,ECX=1):EDX[21] APX_F
CPUID.(EAX=29H,ECX=0):EBX[0] APX_NCI_NDD_NF

Nova Lake, Diamond Rapids

More APX instructions

All 88 APX instructions

Sources

  1. Intel XED v2026.08.23 (commit 0bcb6237345c): forms, encodings, ISA sets, CPUID bits and chip model.
  2. Intel Advanced Performance Extensions (Intel APX) Architecture Specification, revision 7.0 (July 2025)

The tables are derived from Intel XED, Copyright Intel Corporation, licensed under the Apache License 2.0; x86-64.net converted and reformatted them. The text is our own.