PUSH2P instruction (APX)

PUSH2P is PUSH2 with the push-pop acceleration hint: it pushes two 64-bit registers in one instruction and says a matching POP2P will read them back. EVEX.W set to 1 is the only difference in the encoding. The behavior, the 16-byte alignment that raises #GP and the ban on RSP that raises #UD are PUSH2’s, and flags are untouched. As on PUSHP, the hint affects speed alone and a wrong hint cannot change the result.

The pairing is strict by instruction shape: a PUSH2P should meet a POP2P, not two POPP. Intel’s description warns that the optimization works only that way round, so a compiler keeps its prologue and epilogue mirrored.

GCC 14 and Clang 23 at -O2 with -mapxf did so in our builds. Clang saved six registers with pushp rbp, push2p r15, r14, push2p r13, r12, pushp rbx, and restored them with popp rbx, pop2p r12, r13, pop2p r14, r15, popp rbp. Each POP2P names its PUSH2P’s registers in reverse, as the POP2 page explains. The single PUSHP comes first because a function starts with RSP 8 bytes off a 16-byte boundary, and that push aligns it for the pairs.

The specification’s encoding table lists APX_F alone for this instruction, while XED places it in APX_F_N3, which also asks for APX_NCI_NDD_NF; the APX page explains why the two should never differ on an Intel processor.

Forms

Every encoding of PUSH2P that Intel XED knows, one row per XED instruction form (iform). How to read the notation.

Instruction	Encoding	Requires
`PUSH2P r64, r64` PUSH2P_GPR64u64_GPR64u64_APX_N3	`EVEX.LLZ.NP.MAP4.W1 FF /6 ND=1`	APX_F + APX_NCI_NDD_NF

Operation

What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.

if src1.number == 4 or src2.number == 4:
    fault(UD)
a = rsp - 16
if a % 16 != 0:
    fault(GP, 0)
store(a + 8, 64, src1)           # PUSH2 with the hint that a POP2P pops
store(a, 64, src2)               # what it pushes
rsp = a

Not run on a processor: none of these processors has APX.

Operands

What each form reads and writes, as Intel XED records it: the operands of its syntax, in order, and the implicit ones that the syntax does not name. How to read.

Operand	Kind	Action
`PUSH2P r64, r64`
`r64`	explicit	read
`r64`	explicit	read
`stack`	implicit	write
`rSP`	implicit	read, write

Flags

None: XED records no flag that the forms test or change.

Exceptions

The exception class is XED's name for the set of exception conditions that a form follows. How to read.

All forms: APX-EVEX-PP2

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

CPUID requirements and processors of the XED ISA sets above. Alternatives are separated by “or”; processors follow XED’s chip model, whose AMD processors end with Zen 2, and the CPU data of this site for Zen 3 to Zen 6.

ISA set	CPUID	Processors
`APX_F_N3` APX	APX_F + APX_NCI_NDD_NF `CPUID.(EAX=07H,ECX=1):EDX[21]` APX_F `CPUID.(EAX=29H,ECX=0):EBX[0]` APX_NCI_NDD_NF	Nova Lake, Diamond Rapids

More APX instructions

All 88 APX instructions