PUSHA instruction (General-purpose)

PUSHA pushes the eight general-purpose registers in one instruction, in the order AX, CX, DX, BX, SP, BP, SI and DI, so DI ends at the lowest address. The value pushed for SP is the one it had before the instruction. The operand size picks the width: 16 bytes of words, or with PUSHAD 32 bytes of doublewords. PUSHA and PUSHAD are one opcode, 60, and a 66 prefix selects the size that the code segment does not give by default. Intel’s manual leaves it to each assembler whether the mnemonic forces a size; in 32-bit code GNU as 2.44 and Clang 23 encode both pusha and pushad as a plain 60, the 32-bit form, and want pushaw for the 16-bit one. No flag changes.

The frame it leaves is the one POPA reads back, so the pair saves and restores every register in two one-byte instructions, around an interrupt handler for example. Intel’s manual adds a corner of real mode: with SP at 1, 3 or 5, the pushes wrap the stack segment, the #SS that follows cannot be delivered, and the processor shuts down.

Not in 64-bit mode

Opcode 60 raises #UD in 64-bit mode, so the fixture has no case for PUSHA: the probe runs there and lists both forms as not run. There is no 64-bit replacement: code saves registers with PUSH, one at a time, or with APX’s PUSH2, two at a time. Compilers do the same in 32-bit code: in our builds with -m32, a function with __attribute__((interrupt)) saves only the registers it uses, with PUSH, in GCC 14 and Clang 23. GNU as 2.44 and Clang 23 refuse pusha in 64-bit code. AMD’s Zen 5 guide lists PUSHA as microcoded, without a latency.

Forms

Every encoding of PUSHA that Intel XED knows, one row per XED instruction form (iform). How to read the notation.

Instruction	Encoding	Requires
`PUSHA` not in 64-bit mode PUSHA	`66 60`	Base instruction set
`PUSHAD` not in 64-bit mode PUSHAD	`60`	Base instruction set

Operation

What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.

n = OSIZE // 8                   # PUSHA: 2 bytes each; PUSHAD: 4
a = esp                          # a 32-bit stack; SP on a 16-bit one
store(a - n, OSIZE, rAX)
store(a - 2 * n, OSIZE, rCX)
store(a - 3 * n, OSIZE, rDX)
store(a - 4 * n, OSIZE, rBX)
store(a - 5 * n, OSIZE, rSP)     # ESP from before the instruction
store(a - 6 * n, OSIZE, rBP)
store(a - 7 * n, OSIZE, rSI)
store(a - 8 * n, OSIZE, rDI)
esp = a - 8 * n

Not run on a processor: PUSHA does not exist in 64-bit mode, where the probe runs.

Operands

What each form reads and writes, as Intel XED records it: the operands of its syntax, in order, and the implicit ones that the syntax does not name. How to read.

Operand	Kind	Action
`PUSHA` not in 64-bit mode `PUSHAD` not in 64-bit mode
`stack`	implicit	write
`rSP`	implicit	read, write
`AX, EAX`	implicit	read
`CX, ECX`	implicit	read
`DX, EDX`	implicit	read
`BX, EBX`	implicit	read
`SP, ESP`	implicit	read
`BP, EBP`	implicit	read
`SI, ESI`	implicit	read
`DI, EDI`	implicit	read

Flags

None: XED records no flag that the forms test or change.

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

CPUID requirements and processors of the XED ISA sets above. Alternatives are separated by “or”; processors follow XED’s chip model, whose AMD processors end with Zen 2, and the CPU data of this site for Zen 3 to Zen 6.

ISA set	CPUID	Processors
`I186` General-purpose	No CPUID bit: part of the base instruction set.	Every x86-64 processor in XED’s model and Zen 3 to Zen 6
`I386` General-purpose	No CPUID bit: part of the base instruction set.	Every x86-64 processor in XED’s model and Zen 3 to Zen 6

More General-purpose instructions

All 109 General-purpose instructions

Not in 64-bit mode#