PUSHP instruction (APX)

PUSHP is PUSH of a 64-bit register with a hint added: its value will be read back by a matching POPP. The hint lets an APX processor hand the value from the push to the pop internally, without the round trip through memory. The instruction does exactly what PUSH does with the same register: RSP drops by 8 and the register is stored there. Flags are untouched, and the store still happens; the hint is about speed alone, and code runs the same if the processor ignores it.

The encoding is the hint

PUSHP is opcode 50+r, the short register PUSH, under a REX2 prefix with its W bit set. So it needs REX2 even for RAX, which plain PUSH encodes in one byte, and it needs APX enabled (CPUID.(EAX=07H,ECX=1):EDX[21] and XCR0.APX); LOCK and any mode but 64-bit raise #UD. REX2.W also overrides a 66 prefix, so there is no 16-bit form. The other PUSH forms, with a memory operand or an immediate, cannot carry the hint.

The balancing rule

The hint promises that a pop will read this exact stack slot, so both halves must be marked. Function prologues and epilogues fit that rule; arguments pushed for a call do not, since nothing pops them into a register, and should stay plain PUSH. A wrong hint is harmless to results: at worst the optimization turns itself off. For two registers at once, PUSH2P pairs with POP2P, never with two POPP.

In our builds

GCC 14 and Clang 23 at -O2 with -mapxf use PUSHP in prologues, with PUSH2P for the pairs. For a function saving six registers, GCC emitted pushp r15, two push2p and pushp rbx; the first push also brings RSP to the 16-byte alignment that PUSH2P requires. Intel’s list of future features names Diamond Rapids and Nova Lake for APX.

Forms

Every encoding of PUSHP that Intel XED knows, one row per XED instruction form (iform). How to read the notation.

Instruction	Encoding	Requires
`PUSHP r64` PUSHP_GPR64	`REX2.W1 50+r`	APX_F

Operation

What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.

a = rsp - 8                      # PUSH with the hint that a POPP pops
store(a, 64, src)                # what it pushes (APX's PPX); the same
rsp = a                          # operation

Not run on a processor: none of these processors has APX.

Operands

What each form reads and writes, as Intel XED records it: the operands of its syntax, in order, and the implicit ones that the syntax does not name. How to read.

Operand	Kind	Action
`PUSHP r64`
`r64`	explicit	read
`stack`	implicit	write
`rSP`	implicit	read, write

Flags

None: XED records no flag that the forms test or change.

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

CPUID requirements and processors of the XED ISA sets above. Alternatives are separated by “or”; processors follow XED’s chip model, whose AMD processors end with Zen 2, and the CPU data of this site for Zen 3 to Zen 6.

ISA set	CPUID	Processors
`APX_F` APX	APX_F `CPUID.(EAX=07H,ECX=1):EDX[21]` APX_F	Nova Lake, Diamond Rapids

More APX instructions

All 88 APX instructions

The encoding is the hint#

The balancing rule#

In our builds#