PXOR instruction (MMX, SSE2)

PXOR is the bitwise exclusive OR of two 64-bit MMX or 128-bit XMM operands, with the result written over the first. VPXOR covers the VEX form and its uses, and PAND what the legacy encodings share: the SSE2 XMM form, which leaves bits 128 and up of the register as they were (see mixing SSE and AVX) and needs a memory operand aligned to 16 bytes, and the MMX form with its x87 side effects.

The integer zero

pxor xmm0, xmm0 gives zero whatever the register held; on Zen 5, pxor mm3, mm3 cleared an MMX register of all ones. Intel’s optimization manual lists the XMM form with one register twice among the idioms that break the dependency on the old value, which in the Sandy Bridge microarchitecture need no execution unit (Section 3.5.1.7), and uses pxor mm0, mm0 the same way before filling an MMX register with PINSRW (Section 6.4.7, Example 6-11). AMD’s Zen 5 guide lists only the VEX and EVEX VPXOR among its zeroing idioms (Section 2.9.2). Intel’s manual also pairs the zeroing instruction with the data: this one for integers, XORPS for floating point (Section 3.5.1.10).

In our builds at -O2, for the x86-64 baseline and for -march=x86-64-v2, GCC 14 zeroes this way for _mm_setzero_si128, and both GCC and Clang 23 for the accumulators of an integer sum and for the zero that a vector negation subtracts from (see PSUBD). Clang writes XORPS for the intrinsic.

XOR and NOT

With all ones as one operand, PXOR inverts the other: the recorded pxor xmm8, xmm15, with all ones in XMM15, turned 7FFFFFFFFFFFFFFFh into 8000000000000000h and back. SSE has no NOT, so a[i] = ~b[i] is PCMPEQD of a register with itself for the ones, then the XOR, in both compilers. memcmp(p, q, 16) == 0 with x86-64-v2 is two MOVDQU loads, PXOR and PTEST in both; at the baseline GCC compares two quadwords in general-purpose registers instead and Clang uses PCMPEQB and PMOVMSKB. For a[i] = b[i] ^ c[i] over uint32_t, GCC emits PXOR and Clang XORPS.

In the optimization guide

What the optimization guide says about PXOR, a line per claim. Each links to the claim in the guide, with its sources and where they differ.

Out of order

Zeroing and dependency-breaking idioms: The vector registers have idioms of their own: pxor, xorps, xorpd, pandn, andnps, the integer subtractions psub and the comparisons pcmpgt of a register with itself, with their VEX and EVEX forms, which Intel counts for 512-bit registers only unmasked. sources differ

Silvermont to Goldmont Plus

Out-of-order and in-order execution: Silvermont recognizes xor zeroing at 32 bits and for XMM registers, not at 64 bits; Goldmont at 64 bits too.

Skylake to Cooper Lake

Integer execution: xor, sub and the vector pxor, xorps, pandn, psub and pcmpgt of a register with itself zero it without an execution unit, four a cycle, for 32-bit and 64-bit and all vector registers.

Tremont

Integer execution: xor of a register with itself is known not to depend on the register’s old value, for 32-bit and 64-bit, MMX and XMM registers; sub of a register from itself and other idioms are not.

Zen and Zen+

Integer execution: Register-to-register moves of 32-bit and 64-bit general registers and of XMM registers, and xchg of general registers, take no execution cycle, while a YMM move renames only its lower half and moves the upper one in a pipe. sources differ

Zen 2

Integer execution: Register-to-register moves of general registers of 32 and 64 bits, xchg of them and moves of whole XMM and YMM registers take no execution cycle, where Zen 1 moves the upper half of a YMM register in a pipe. sources differ

Forms

Every encoding of PXOR that Intel XED knows, one row per XED instruction form (iform). How to read the notation.

Instruction	Encoding	Requires
`PXOR mm, m64` PXOR_MMXq_MEMq	`NP 0F EF /r`	MMX
`PXOR mm, mm` PXOR_MMXq_MMXq	`NP 0F EF /r`	MMX
`PXOR xmm, m128` PXOR_XMMdq_MEMdq	`66 0F EF /r`	SSE2
`PXOR xmm, xmm` PXOR_XMMdq_XMMdq	`66 0F EF /r`	SSE2

Data flow

Where the elements of the sources go, element 0 on the right; results that depend on a control value are drawn for an example. How to read.

Element-wise: each quadword of the result comes from the quadword in the same place in each source.

Every quadword works alike: 1 and 2 quadwords in the mm and xmm forms.

Result quadword i comes from quadword i of xmm1 and xmm2. Result quadwords 1 to 0: a1^b1, a0^b0.

Operation

What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.

PXOR mm, mm/m64

i = 0
mm1.q[i] = mm1.q[i] ^ src2.q[i]
# x87: TOP = 0, all tags valid, bits 79:64 of mm1's register all ones

Run on AMD Zen 5 (EPYC 9645): 2 cases.

PXOR xmm, xmm/m128

for i in range(2):
    xmm1.q[i] = xmm1.q[i] ^ src2.q[i]
# bits 128 and up of the register are unchanged

Run on AMD Zen 5 (EPYC 9645): 2 cases.

Operands

What each form reads and writes, as Intel XED records it: the operands of its syntax, in order, and the implicit ones that the syntax does not name. How to read.

Operand	Kind	Action
`PXOR mm, mm/m64`
`mm`	explicit	read, write
`mm/m64`	explicit	read
`PXOR xmm, xmm/m128`
`xmm`	explicit	read, write
`xmm/m128`	explicit	read

Flags

None: XED records no flag that the forms test or change.

Exceptions

The exception class is XED's name for the set of exception conditions that a form follows. How to read.

PXOR mm, mm/m64: mmx-mem
PXOR xmm, xmm/m128: SSE_TYPE_4

Attributes

What else XED records about the forms. How to read.

PXOR mm, mm/m64: may abort a TSX transaction
PXOR xmm, m128: aligned memory operand

Intrinsics

The C intrinsics of Clang 23.1.2 that compile to PXOR, each with the form it compiles to and the Clang options it needs. The forms come from compiling every intrinsic and decoding the result with Intel XED; all intrinsics A–Z explains the method.

Intrinsic	Compiles to
`_mm_xor_pd` `__m128d _mm_xor_pd(__m128d __a, __m128d __b)`	`PXOR xmm, xmm` Legacy -msse2
`_mm_xor_si128` `__m128i _mm_xor_si128(__m128i __a, __m128i __b)`	`PXOR xmm, xmm` Legacy -msse2
`_mm_xor_si64` `__m64 _mm_xor_si64(__m64 __m1, __m64 __m2)`	`PXOR xmm, xmm` Legacy -msse2

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

CPUID requirements and processors of the XED ISA sets above. Alternatives are separated by “or”; processors follow XED’s chip model, whose AMD processors end with Zen 2, and the CPU data of this site for Zen 3 to Zen 6.

ISA set	CPUID	Processors
`PENTIUMMMX` MMX	MMX `CPUID.01H:EDX[23]` MMX	Every x86-64 processor in XED’s model and Zen 3 to Zen 6
`SSE2` SSE2	SSE2 `CPUID.01H:EDX[26]` SSE2	Every x86-64 processor in XED’s model and Zen 3 to Zen 6

More MMX instructions

All 47 MMX instructions

More SSE2 instructions

All 124 SSE2 instructions

The integer zero#

XOR and NOT#