RCL

RCL rotates its operand left through the carry flag: CF and the operand form one ring of 9, 17, 33 or 65 bits, so the bit leaving the top goes into CF and the old CF comes in at bit 0. By one bit, it is a shift left that brings CF in, which is how assembly shifts a number wider than a register: SHL on the lowest word, then RCL by 1 on each word above, each taking in the bit the one below pushed out. RCR is its mirror image, and ROL rotates without CF.

A ring one bit wider#

The count, 1, an immediate or CL, is masked to 5 bits, or 6 for a 64-bit operand, as for the other shifts and rotates. Since the ring is one bit wider than the operand, the byte and word forms then take it modulo 9 and 17: an RCL of AL by 9 leaves AL and CF as they were. A 32- or 64-bit operand never makes a full turn, and a masked count of 0 changes no flag.

Only CF and OF#

Both manuals define OF for a count of 1 alone, as the exclusive or of the result’s top bit and the new CF. In the 99 recorded cases with larger counts, Zen 5 set OF by the same rule, even after a whole turn of the ring, which left the value and CF alone but still changed OF; code should not rely on it.

In compiled code#

Neither GCC 14 nor Clang 23 used RCL at -O2 in our builds. For a 128-bit x << 1, GCC adds each half to itself with ADD and ADC, and Clang uses SHLD and LEA; a loop shifting an array of words left by one bit kept the carried bit in a register.

Cost and other forms#

AMD’s Zen 5 guide lists RCL with an immediate count as one macro-op with a latency of one cycle, and as microcoded with the count in CL. Intel’s optimization manual names RCL, with MUL and SHLD, among the instructions of the single slow-integer unit of Skylake, Ice Lake and Golden Cove (Tables 2-14, 2-7 and 2-4). APX adds forms with a new destination register, but none that leaves the flags alone.

Forms

Latency and throughput

Operation

What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.

a = dest.read()
n = count & (0x3F if OSIZE == 64 else 0x1F)   # the count is masked,
k = n % (OSIZE + 1)              # then taken modulo OSIZE + 1: CF is a
                                 # bit of the rotation (9 for 8 bits)
x = cf << OSIZE | a              # CF above the operand
y = x << k | x >> (OSIZE + 1 - k)
r = low(y)
if n != 0:                       # a count of 0 changes no flag
    c = y >> OSIZE & 1           # the bit rotated out of the top;
    cf = c                       # CF as it was when k is 0
    of = msb(r) ^ c if n == 1 else UNDEFINED
dest.write(r)                    # even for a count of 0, a 32-bit register
                                 # gets bits 63:32 cleared

a = src.read()
n = count & (0x3F if OSIZE == 64 else 0x1F)   # the count is masked,
k = n % (OSIZE + 1)              # then taken modulo OSIZE + 1: CF is a
                                 # bit of the rotation (9 for 8 bits)
x = cf << OSIZE | a              # CF above the operand
y = x << k | x >> (OSIZE + 1 - k)
r = low(y)
if n != 0:                       # a count of 0 changes no flag
    c = y >> OSIZE & 1           # the bit rotated out of the top;
    cf = c                       # CF as it was when k is 0
    of = msb(r) ^ c if n == 1 else UNDEFINED
dest.write(r)                    # the new destination: bits 63:OSIZE
                                 # cleared, even for 8 and 16 bits

Operands

Flags

Exceptions

The exception class is XED's name for the set of exception conditions that a form follows. How to read.

Legacy forms

none in XED

EVEX forms

APX-EVEX-INT

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

More General-purpose instructions

• LSS
• MOV
• MOVS
• MOVSX
• MOVSXD
• MOVZX
• MUL
• NEG
• NOP
• NOT
• OR
• OUT
• OUTS
• PAUSE
• POP
• POPA
• POPF
• PUSH
• PUSHA
• PUSHF
• RCR
• RET
• ROL
• ROR
• SALC
• SAR
• SBB
• SCAS
• SETcc
• SHL
• SHLD
• SHR
• SHRD
• STC
• STD
• STI
• STOS
• SUB
• TEST
• UD0

All 109 General-purpose instructions

More APX instructions

• LDTILECFG
• LZCNT
• MOVBE
• MOVDIR64B
• MOVDIRI
• MOVRS
• MUL
• MULX
• NEG
• NOT
• OR
• PDEP
• PEXT
• POP2
• POP2P
• POPCNT
• POPP
• PUSH2
• PUSH2P
• PUSHP
• RCR
• RDMSR
• ROL
• ROR
• RORX
• SAR
• SARX
• SBB
• SETcc
• SHL
• SHLD
• SHLX
• SHR
• SHRD
• SHRX
• STTILECFG
• SUB
• TILELOADD
• TILELOADDRS
• TILELOADDRST1

All 88 APX instructions