RCPSS instruction (SSE)

RCPSS estimates 1/x for the low single of its source and keeps singles 1 to 3 of the destination. Intel’s manual bounds the relative error of the estimate by 1.5 times 2^-12, about 11 correct bits, and leaves the bits themselves to the processor; the page’s Operation section accepts any result within that bound and gives the worst error among Zen 5’s recorded estimates. VRCPPS covers the special inputs, which this form treats the same way, and VRCPSS is the VEX form. The recorded cases:

1.40479597e-38 (0098F7FFh), just above the smallest normal single, gave 7.12071591e37 (7E564800h), in a register and from memory alike;
the largest denormal, 007FFFFFh, with DAZ set, and the smallest, 00000001h, with DAZ clear, both gave +infinity: a denormal input counts as zero either way;
2^127, with FTZ set, gave +0, its reciprocal being below the normal range (VRCPPS shows the same with FTZ clear);
the signaling NaN 7F812345h came back quiet as 7FC12345h, with every exception unmasked and no flag set;
singles 1 to 3 kept their values in every case.

Only on request

In our builds at -O2, GCC 14 and Clang 23 never pick the estimate unasked: they compile 1.0f / x and a / b over floats to DIVSS even with -ffast-math. Adding -mrecip lets both replace the division with RCPSS and one Newton-Raphson step: for 1.0f / x, GCC computes 2r - xr^2 and Clang r + r(1 - xr), and a / b folds the multiplication by a into the sequence. The result is close to single precision but can differ in its last bits between processors, as the estimate does. The intrinsic _mm_rcp_ss gives the bare estimate in both.

AMD’s latency spreadsheet for Zen 5 lists RCPSS at 4 cycles on pipes FP1 and FP2, and its guide names it among the merging instructions that skip the wait for the old destination when its upper bits are known to be zero (Section 2.11.5); SQRTSS explains that merge. The legacy form keeps bits 255:128 (see mixing SSE and AVX), and its memory form reads four bytes at any alignment. RCPPS is the packed form and RSQRTSS the reciprocal square root.

Forms

Every encoding of RCPSS that Intel XED knows, one row per XED instruction form (iform). How to read the notation.

Instruction	Encoding	Requires
`RCPSS xmm, m32` RCPSS_XMMss_MEMss	`F3 0F 53 /r`	SSE
`RCPSS xmm, xmm` RCPSS_XMMss_XMMss	`F3 0F 53 /r`	SSE

Data flow

Where the elements of the sources go, element 0 on the right; results that depend on a control value are drawn for an example. How to read.

Scalar: only the low single is computed; the other singles come from xmm1.

Result single 0 is computed from single 0 of xmm2; singles 3 to 1 are those of xmm1. Result singles 3 to 0: a3, a2, a1, r0.

Operation

What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.

xmm1.f32[0] = rcp(src2.f32[0])
# xmm1.d[1] to [3] keep their values
# rcp: 1/a within 1.5 * 2^-12; Zen 5's 2
# recorded results: 1.2915 * 2^-12 at most
# a denormal is a zero, and so is a result below 2^-126
# (in Zen 5's cases, from |a| = 2^127 up), whatever
# MXCSR says; no flags
# bits 128 and up of the register are unchanged

Run on AMD Zen 5 (EPYC 9645): 6 cases.

Operands

What each form reads and writes, as Intel XED records it: the operands of its syntax, in order, and the implicit ones that the syntax does not name. How to read.

Operand	Kind	Action
`RCPSS xmm, xmm/m32`
`xmm`	explicit	read, write
`xmm/m32`	explicit	read

Flags

None: XED records no flag that the forms test or change.

Exceptions

The exception class is XED's name for the set of exception conditions that a form follows. How to read.

All forms: SSE_TYPE_5

Intrinsics

The C intrinsics of Clang 23.1.2 that compile to RCPSS, each with the form it compiles to and the Clang options it needs. The forms come from compiling every intrinsic and decoding the result with Intel XED; all intrinsics A–Z explains the method.

Intrinsic	Compiles to
`_mm_rcp_ss` `__m128 _mm_rcp_ss(__m128 __a)`	`RCPSS xmm, xmm` Legacy -msse

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

CPUID requirements and processors of the XED ISA sets above. Alternatives are separated by “or”; processors follow XED’s chip model, whose AMD processors end with Zen 2, and the CPU data of this site for Zen 3 to Zen 6.

ISA set	CPUID	Processors
`SSE` SSE	SSE `CPUID.01H:EDX[25]` SSE	Every x86-64 processor in XED’s model and Zen 3 to Zen 6

More SSE instructions

All 65 SSE instructions

Only on request#