RCR

RCR rotates its operand right through the carry flag: CF and the operand form one ring of 9, 17, 33 or 65 bits, so the bit leaving bit 0 goes into CF and the old CF comes in at the top. By one bit, it is a right shift that brings CF in at the top, which is how assembly shifts a number wider than a register right: SHR, or SAR for a signed number, on the highest word, then RCR by 1 on each word below. The same step halves a sum that overflowed: after an ADD that set CF, RCR by 1 gives the true average. RCL is the mirror image, and its page gives the rules for the count, which RCR shares.

OF, and the counts that do nothing#

Both manuals define OF for a count of 1 alone, as the exclusive or of the result’s two top bits, that is, the old top bit XOR the old CF. In the 97 recorded cases with a larger masked count, Zen 5 set OF by the same rule. Eight were whole turns, a byte by 9, 18 or 27 or a word by 17, which left the value and CF as they were but changed OF in five; code should not rely on it.

A masked count of 0 changes no flag, and in its 37 such cases Zen 5 changed none. It still wrote a 32-bit register: by 0, 32 or 64, RCR cleared bits 63:32, as any write of a 32-bit register does.

In compiled code#

Neither GCC 14 nor Clang 23 used RCR at -O2 in our builds. A 128-bit x >> 1 became SHRD and SHR (SAR when signed). The average of two 64-bit numbers through a 128-bit sum became ADD, ADC and SHRD in GCC, while Clang computed (a & b) + ((a ^ b) >> 1), which needs no carry.

Cost and other forms#

AMD’s Zen 5 guide lists RCR with an immediate count as one macro-op with a latency of one cycle, and as microcoded with the count in CL. APX adds forms with a new destination register, but none that leaves the flags alone.

Forms

Latency and throughput

Operation

What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.

a = dest.read()
n = count & (0x3F if OSIZE == 64 else 0x1F)   # the count is masked,
k = n % (OSIZE + 1)              # then taken modulo OSIZE + 1: CF is a
                                 # bit of the rotation (9 for 8 bits)
x = cf << OSIZE | a              # CF above the operand
y = x >> k | x << (OSIZE + 1 - k)
r = low(y)
if n != 0:                       # a count of 0 changes no flag
    cf = y >> OSIZE & 1          # the bit rotated out of bit 0; CF as
                                 # it was when k is 0
    flip = msb(r) ^ (r >> (OSIZE - 2) & 1)
    of = flip if n == 1 else UNDEFINED   # the top two bits differ
dest.write(r)                    # even for a count of 0, a 32-bit register
                                 # gets bits 63:32 cleared

a = src.read()
n = count & (0x3F if OSIZE == 64 else 0x1F)   # the count is masked,
k = n % (OSIZE + 1)              # then taken modulo OSIZE + 1: CF is a
                                 # bit of the rotation (9 for 8 bits)
x = cf << OSIZE | a              # CF above the operand
y = x >> k | x << (OSIZE + 1 - k)
r = low(y)
if n != 0:                       # a count of 0 changes no flag
    cf = y >> OSIZE & 1          # the bit rotated out of bit 0; CF as
                                 # it was when k is 0
    flip = msb(r) ^ (r >> (OSIZE - 2) & 1)
    of = flip if n == 1 else UNDEFINED   # the top two bits differ
dest.write(r)                    # the new destination: bits 63:OSIZE
                                 # cleared, even for 8 and 16 bits

Operands

Flags

Exceptions

The exception class is XED's name for the set of exception conditions that a form follows. How to read.

Legacy forms

none in XED

EVEX forms

APX-EVEX-INT

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

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All 88 APX instructions