x86-64.net

Instruction

RDMSR

Reads a model-specific register into EDX:EAX, or with MSR_IMM into any 64-bit register from an MSR number given as an immediate; allowed only in ring 0.

Extensions
Forms
3 (1 Legacy, 1 VEX, 1 EVEX)
Data
Intel XED v2026.08.23

Forms

Every encoding of RDMSR that Intel XED knows, one row per XED instruction form (iform). How to read the notation.
InstructionEncodingRequires
RDMSR RDMSR0F 32Base instruction set
RDMSR r64, imm32 64-bit mode only RDMSR_GPR64u64_IMM32VEX.LZ.F2.MAP7.WIG F6 /0 idMSR_IMM
RDMSR r64, imm32 RDMSR_GPR64u64_IMM32_APXEVEX.LLZ.F2.MAP7.WIG F6 /0 idAPX_F + MSR_IMM

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

CPUID requirements and processors of the XED ISA sets above. Alternatives are separated by “or”; processors follow XED’s chip model, which covers AMD processors up to Zen 2.
ISA setCPUIDProcessors in XED
PENTIUMREAL

No CPUID bit: part of the base instruction set.

Every x86-64 processor in XED’s model
MSR_IMM

MSR_IMM
CPUID.(EAX=07H,ECX=1):ECX[5] MSR_IMM

Clearwater Forest
APX_F_MSR_IMM

APX_F + MSR_IMM
CPUID.(EAX=07H,ECX=1):EDX[21] APX_F
CPUID.(EAX=07H,ECX=1):ECX[5] MSR_IMM

None yet: XED lists these instructions only under its placeholder for future processors.

More MSR_IMM instructions

More APX instructions

All 88 APX instructions

Sources

  1. Intel XED v2026.08.23 (commit 0bcb6237345c): forms, encodings, ISA sets, CPUID bits and chip model.
  2. Intel 64 and IA-32 Architectures Software Developer's Manual, Volume 2 (325383-092, June 2026)
  3. Intel Advanced Performance Extensions (Intel APX) Architecture Specification, revision 7.0 (July 2025)

The tables are derived from Intel XED, Copyright Intel Corporation, licensed under the Apache License 2.0; x86-64.net converted and reformatted them. The text is our own.