RDPRU instruction (RDPRU)

In the optimization guide

What the optimization guide says about RDPRU, a line per claim. Each links to the claim in the guide, with its sources and where they differ.

Measuring

Core cycles, reference cycles and the TSC: On AMD’s processors from Zen 3 on, RDPRU reads APERF and MPERF at any privilege level unless CR4.TSD is set.

Forms

Every encoding of RDPRU that Intel XED knows, one row per XED instruction form (iform). How to read the notation.

Instruction	Encoding	Requires
`RDPRU` RDPRU	`0F 01 FD`	RDPRU

Latency and throughput

What the scheduling models of LLVM 23.1.2 give for each form, not measurements: latency / reciprocal throughput in cycles, the ports under them. A row is a model, or models that agree; a dash, a form that its processors lack. Memory forms: latency from the address, ports without the load and store units. Which processors each model covers.

Model	`RDPRU`
Zen 2	100 / 0.25
Zen 3, Zen 4	100 / 25ALU0 ALU1 ALU2 ALU3

Operation

What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.

if CPL > 0 and cr4 >> 2 & 1:     # CR4.TSD: #UD, where RDTSC raises
    fault(UD)                    # #GP
v = pru(ecx)                     # the processor's counts: ECX 0, MPERF;
                                 # 1, APERF; 0 past the highest number
                                 # it knows (CPUID Fn8000_0008_EDX[31:16])
edx = v >> 32                    # bits 63:32 of RDX and RAX cleared
eax = low(v, 32)
# AMD's manual lists CF as written and OF, SF, ZF, AF and PF as
# cleared, without saying what CF holds; XED records no flags

Not run on a processor: the Zen 5 guest that ran the probe does not report RDPRU in CPUID, and it is an AMD instruction.

Operands

What each form reads and writes, as Intel XED records it: the operands of its syntax, in order, and the implicit ones that the syntax does not name. How to read.

Operand	Kind	Action
`RDPRU`
`EDX`	implicit	write
`EAX`	implicit	write
`ECX`	implicit	read

Flags

None: XED records no flag that the forms test or change.

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

CPUID requirements and processors of the XED ISA sets above. Alternatives are separated by “or”; processors follow XED’s chip model, whose AMD processors end with Zen 2, and the CPU data of this site for Zen 3 to Zen 6.

ISA set	CPUID	Processors
`RDPRU` RDPRU	RDPRU `CPUID.80000008H:EBX[4]` RDPRU	Zen 2, Zen 3, Zen 4, Zen 5, Zen 6