Instruction
RMPADJUST
Changes the permissions of a guest page for a less privileged VMPL in the reverse map (RMP); SEV-SNP.
An AMD extension: Intel processors do not have this instruction.
- Extensions
- Forms
- 1 (1 Legacy)
- Data
- Intel XED v2026.08.23
Forms
| Instruction | Encoding | Requires |
|---|---|---|
RMPADJUST RAX, RCX, RDX 64-bit mode only
RMPADJUST_RAX_RCX_RDX | F3 0F 01 FE | SNP |
Operation
What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.
if not snp_active:
fault(UD) # outside an SNP-active guest
if CPL > 0:
fault(GP, 0)
va = addr.read() & ~0xFFF # RAX: the page's virtual address
big = size.read() & 1 # RCX bit 0: a 2-MB page
d = target.read() # RDX
t = d & 0xFF # a VMPL, and the permission mask
p = d >> 8 & 0xFF # it is to have
if big and va >> 12 & 0x1FF:
eax = 1 # FAIL_INPUT: off a 2-MB boundary
elif t <= vmpl:
eax = 2 # FAIL_PERMISSION: a VMPL changes
# only those less privileged
else:
gpa = guest_pa(va) # the guest's page tables, then the
spa = system_pa(gpa) # nested ones
if not in_rmp(spa):
vm_exit(0x400) # #VMEXIT(NPF): no RMP entry
r = rmp(spa)
g = r >> 96 & 0xFFFFFFFF # its ASID, and 2-MB page size
s2m = r >> 72 & 1
bad = r >> 80 & 1 or not r >> 64 & 1
if low(r, 64) != gpa or g != asid:
bad = 1 # another guest's page, or another
# address in it
if s2m != npt_large(gpa):
bad = 1 # not the nested page's size
if s2m and not big:
bad = 1 # 4 KB of a 2-MB page
if bad:
vm_exit(0x400) # #VMEXIT(NPF)
if not r >> 128 & 1:
fault(VC, 0x404) # PAGE_NOT_VALIDATED
own = r >> 136 + 8 * vmpl & 0xFF
if big and not s2m:
eax = 6 # FAIL_SIZEMISMATCH
elif p & ~own:
eax = 2 # FAIL_PERMISSION: more than the
# VMPL has itself
else:
if vmpl == 0: # VMSA from RDX bit 16, at VMPL 0
r = r & ~(1 << 129)
r = r | (d >> 16 & 1) << 129
at = 136 + 8 * t
r = r & ~(0xFF << at)
set_rmp(spa, r | p << at)
eax = 0 # SUCCESS
of = zf = af = pf = sf = UNDEFINEDRun on AMD Zen 5 (EPYC 9645): 2 cases. Its cases ran where CPUID reported no SEV-SNP, and every one raised an exception.
Operands
| Operand | Kind | Action |
|---|---|---|
RMPADJUST RAX, RCX, RDX 64-bit mode only | ||
RAX | explicit | read, write |
RCX | explicit | read |
RDX | explicit | read |
RFLAGS | implicit | write |
Flags
| OF | SF | ZF | AF | PF |
|---|---|---|---|---|
| All forms | ||||
| M | M | M | M | M |
Attributes
What else XED records about the forms. How to read.
- All forms
- privileged: CPL 0 only
CPUID and processors
Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.
More SEV-SNP instructions
Sources
- Intel XED v2026.08.23 (commit
0bcb6237345c): forms, encodings, operands, flags, exception classes, attributes, ISA sets, CPUID bits and chip model. - The CPU data of x86-64.net: Zen 3 to Zen 6, from GCC’s
-marchfeature sets and AMD’s Processor Programming References, which the page of each processor cites. - AMD64 Architecture Programmer's Manual, Volume 3: General-Purpose and System Instructions (24594, rev. 3.36, March 2024), Wayback Machine copy of AMD's PDF
- AMD64 Architecture Programmer's Manual, Volume 2: System Programming (24593, rev. 3.42, March 2024), Wayback Machine copy of AMD's PDF
The tables are derived from Intel XED, Copyright Intel Corporation, licensed under the Apache License 2.0; x86-64.net converted and reformatted them. The text is our own.