ROL

ROL rotates its operand left: every bit moves up by the count, and the bits pushed out at the top come back in at the bottom, so none is lost. ROR rotates the other way, and a rotate left by k equals a rotate right by the operand’s width minus k. C has no rotate operator; GCC 14 and Clang 23 at -O2 recognize the pattern instead: (x << 7) | (x >> 25) on a uint32_t becomes rol eax, 7, and (x << 8) | (x >> 8) on a uint16_t, which swaps its two bytes, becomes rol ax, 8.

A count in a variable#

(x << n) | (x >> (32 - n)) is undefined in C for n = 0, and (x << (n & 31)) | (x >> (-n & 31)) is not; both compilers turn either into one rol eax, cl, since the processor masks the count itself: to 5 bits, or 6 for a 64-bit operand. An 8- or 16-bit rotate then takes the masked count modulo its width, so rol al, cl with CL = 8 leaves AL as it was.

Only CF and OF#

A rotate writes no flag but CF and OF. CF receives the bit that landed in bit 0, the last one to leave the top; OF is defined only for a count of 1. A masked count of 0 changes neither, but a count that is a multiple of the width is not 0: Zen 5, rotating a byte by 8 or a word by 16, left the value alone and still copied its bit 0 into CF. RCL and RCR rotate through CF instead.

Other forms and speed#

RORX from BMI2 rotates right by an immediate into another register and leaves the flags alone; with -march=x86-64-v3, both compilers use it for constant rotates either way, turning the rotate left by 7 into rorx eax, edi, 25. APX adds forms with a new destination and forms that leave the flags unchanged (NF).

Intel’s optimization manual says that in Sandy Bridge a rotate by CL takes three micro-ops, one of which may be dropped when no later instruction reads its flags (Section 3.5.1.5). The instruction table of AMD’s Zen 5 guide lists ROL and ROR as single macro-ops with a latency of one cycle.

In the optimization guide

What the optimization guide says about ROL, a line per claim. Each links to the claim in the guide, with its sources and where they differ.

Out of order

• Partial register and flag writes: A shift or rotate by CL leaves the flags alone when the count is zero, which is known only when it runs, so it depends on the old flags too.

Forms

Latency and throughput

Operation

What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.

a = dest.read()
n = count & (0x3F if OSIZE == 64 else 0x1F)   # the count is masked,
k = n % OSIZE                    # then taken modulo the operand size
r = low(a << k | a >> (OSIZE - k))
if n != 0 and not nf:            # a count of 0 changes no flag; NF=1
                                 # (APX) none at all
    cf = r & 1                   # the bit rotated into bit 0, even
                                 # when k is 0
    flip = msb(r) ^ (r & 1)
    of = flip if n == 1 else UNDEFINED   # the top bit and CF differ
dest.write(r)                    # even for a count of 0, a 32-bit register
                                 # gets bits 63:32 cleared

a = src.read()
n = count & (0x3F if OSIZE == 64 else 0x1F)   # the count is masked,
k = n % OSIZE                    # then taken modulo the operand size
r = low(a << k | a >> (OSIZE - k))
if n != 0 and not nf:            # a count of 0 changes no flag; NF=1
                                 # none at all
    cf = r & 1                   # the bit rotated into bit 0, even
                                 # when k is 0
    flip = msb(r) ^ (r & 1)
    of = flip if n == 1 else UNDEFINED   # the top bit and CF differ
dest.write(r)                    # the new destination: bits 63:OSIZE
                                 # cleared, even for 8 and 16 bits

Operands

Flags

Exceptions

The exception class is XED's name for the set of exception conditions that a form follows. How to read.

Legacy forms

none in XED

EVEX forms

APX-EVEX-INT

Intrinsics

The C intrinsics of Clang 23.1.2 that compile to ROL, each with the form it compiles to and the Clang options it needs. The forms come from compiling every intrinsic and decoding the result with Intel XED; all intrinsics A–Z explains the method.

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

More General-purpose instructions

• MOVSX
• MOVSXD
• MOVZX
• MUL
• NEG
• NOP
• NOT
• OR
• OUT
• OUTS
• PAUSE
• POP
• POPA
• POPF
• PUSH
• PUSHA
• PUSHF
• RCL
• RCR
• RET
• ROR
• SALC
• SAR
• SBB
• SCAS
• SETcc
• SHL
• SHLD
• SHR
• SHRD
• STC
• STD
• STI
• STOS
• SUB
• TEST
• UD0
• UD1
• UD2
• UDB

All 109 General-purpose instructions

More APX instructions

• MOVDIR64B
• MOVDIRI
• MOVRS
• MUL
• MULX
• NEG
• NOT
• OR
• PDEP
• PEXT
• POP2
• POP2P
• POPCNT
• POPP
• PUSH2
• PUSH2P
• PUSHP
• RCL
• RCR
• RDMSR
• ROR
• RORX
• SAR
• SARX
• SBB
• SETcc
• SHL
• SHLD
• SHLX
• SHR
• SHRD
• SHRX
• STTILECFG
• SUB
• TILELOADD
• TILELOADDRS
• TILELOADDRST1
• TILELOADDT1
• TILESTORED
• TZCNT

All 88 APX instructions