x86-64.net

Instruction

ROL

Rotates an operand left; APX adds three-operand forms and forms that leave the flags unchanged.

Extensions
Forms
48 (12 Legacy, 36 EVEX)
Data
Intel XED v2026.08.23

Forms

Every encoding of ROL that Intel XED knows, one row per XED instruction form (iform). How to read the notation.
InstructionEncodingRequires
ROL m8, imm8 ROL_MEMb_IMMbC0 /0 ibBase instruction set
ROL r8, imm8 ROL_GPR8_IMMbC0 /0 ibBase instruction set
ROL m16/32/64, imm8 ROL_MEMv_IMMbC1 /0 ibBase instruction set
ROL r16/32/64, imm8 ROL_GPRv_IMMbC1 /0 ibBase instruction set
ROL m8, imm8 ROL_MEMb_ONED0 /0Base instruction set
ROL r8, imm8 ROL_GPR8_ONED0 /0Base instruction set
ROL m16/32/64, imm8 ROL_MEMv_ONED1 /0Base instruction set
ROL r16/32/64, imm8 ROL_GPRv_ONED1 /0Base instruction set
ROL m8, CL ROL_MEMb_CLD2 /0Base instruction set
ROL r8, CL ROL_GPR8_CLD2 /0Base instruction set
ROL m16/32/64, CL ROL_MEMv_CLD3 /0Base instruction set
ROL r16/32/64, CL ROL_GPRv_CLD3 /0Base instruction set
ROL r8, imm8 ROL_GPR8i8_IMM8_APXEVEX.LLZ.NP.MAP4.WIG C0 /0 ibAPX_F
ROL m8, imm8 ROL_MEMi8_IMM8_APXEVEX.LLZ.NP.MAP4.WIG C0 /0 ibAPX_F
ROL r8, imm8 NF ROL_GPR8i8_IMM8_APX_N3EVEX.LLZ.NP.MAP4.WIG C0 /0 ib NF=1APX_F + APX_NCI_NDD_NF
ROL m8, imm8 NF ROL_MEMi8_IMM8_APX_N3EVEX.LLZ.NP.MAP4.WIG C0 /0 ib NF=1APX_F + APX_NCI_NDD_NF
ROL r16/32/64, r16/32/64, imm8 NDD NF optional ROL_GPRv_GPRv_IMM8_APX_N3EVEX.LLZ.NP.MAP4.SCALABLE C1 /0 ib ND=1 NF=0/1APX_F + APX_NCI_NDD_NF
ROL r16/32/64, m16/32/64, imm8 NDD NF optional ROL_GPRv_MEMv_IMM8_APX_N3EVEX.LLZ.NP.MAP4.SCALABLE C1 /0 ib ND=1 NF=0/1APX_F + APX_NCI_NDD_NF
ROL r8, imm8 ROL_GPR8i8_ONE_APXEVEX.LLZ.NP.MAP4.WIG D0 /0APX_F
ROL m8, imm8 ROL_MEMi8_ONE_APXEVEX.LLZ.NP.MAP4.WIG D0 /0APX_F
ROL r8, imm8 NF ROL_GPR8i8_ONE_APX_N3EVEX.LLZ.NP.MAP4.WIG D0 /0 NF=1APX_F + APX_NCI_NDD_NF
ROL m8, imm8 NF ROL_MEMi8_ONE_APX_N3EVEX.LLZ.NP.MAP4.WIG D0 /0 NF=1APX_F + APX_NCI_NDD_NF
ROL r8, r8, imm8 NDD NF optional ROL_GPR8i8_GPR8i8_ONE_APX_N3EVEX.LLZ.NP.MAP4.WIG D0 /0 ND=1 NF=0/1APX_F + APX_NCI_NDD_NF
ROL r8, m8, imm8 NDD NF optional ROL_GPR8i8_MEMi8_ONE_APX_N3EVEX.LLZ.NP.MAP4.WIG D0 /0 ND=1 NF=0/1APX_F + APX_NCI_NDD_NF
ROL r16/32/64, imm8 ROL_GPRv_ONE_APXEVEX.LLZ.NP.MAP4.SCALABLE D1 /0APX_F
ROL m16/32/64, imm8 ROL_MEMv_ONE_APXEVEX.LLZ.NP.MAP4.SCALABLE D1 /0APX_F
ROL r16/32/64, imm8 NF ROL_GPRv_ONE_APX_N3EVEX.LLZ.NP.MAP4.SCALABLE D1 /0 NF=1APX_F + APX_NCI_NDD_NF
ROL m16/32/64, imm8 NF ROL_MEMv_ONE_APX_N3EVEX.LLZ.NP.MAP4.SCALABLE D1 /0 NF=1APX_F + APX_NCI_NDD_NF
ROL r16/32/64, r16/32/64, imm8 NDD NF optional ROL_GPRv_GPRv_ONE_APX_N3EVEX.LLZ.NP.MAP4.SCALABLE D1 /0 ND=1 NF=0/1APX_F + APX_NCI_NDD_NF
ROL r16/32/64, m16/32/64, imm8 NDD NF optional ROL_GPRv_MEMv_ONE_APX_N3EVEX.LLZ.NP.MAP4.SCALABLE D1 /0 ND=1 NF=0/1APX_F + APX_NCI_NDD_NF
ROL r8, CL ROL_GPR8i8_CL_APXEVEX.LLZ.NP.MAP4.WIG D2 /0APX_F
ROL m8, CL ROL_MEMi8_CL_APXEVEX.LLZ.NP.MAP4.WIG D2 /0APX_F
ROL r8, CL NF ROL_GPR8i8_CL_APX_N3EVEX.LLZ.NP.MAP4.WIG D2 /0 NF=1APX_F + APX_NCI_NDD_NF
ROL m8, CL NF ROL_MEMi8_CL_APX_N3EVEX.LLZ.NP.MAP4.WIG D2 /0 NF=1APX_F + APX_NCI_NDD_NF
ROL r8, r8, CL NDD NF optional ROL_GPR8i8_GPR8i8_CL_APX_N3EVEX.LLZ.NP.MAP4.WIG D2 /0 ND=1 NF=0/1APX_F + APX_NCI_NDD_NF
ROL r8, m8, CL NDD NF optional ROL_GPR8i8_MEMi8_CL_APX_N3EVEX.LLZ.NP.MAP4.WIG D2 /0 ND=1 NF=0/1APX_F + APX_NCI_NDD_NF
ROL r16/32/64, CL ROL_GPRv_CL_APXEVEX.LLZ.NP.MAP4.SCALABLE D3 /0APX_F
ROL m16/32/64, CL ROL_MEMv_CL_APXEVEX.LLZ.NP.MAP4.SCALABLE D3 /0APX_F
ROL r16/32/64, CL NF ROL_GPRv_CL_APX_N3EVEX.LLZ.NP.MAP4.SCALABLE D3 /0 NF=1APX_F + APX_NCI_NDD_NF
ROL m16/32/64, CL NF ROL_MEMv_CL_APX_N3EVEX.LLZ.NP.MAP4.SCALABLE D3 /0 NF=1APX_F + APX_NCI_NDD_NF
ROL r16/32/64, r16/32/64, CL NDD NF optional ROL_GPRv_GPRv_CL_APX_N3EVEX.LLZ.NP.MAP4.SCALABLE D3 /0 ND=1 NF=0/1APX_F + APX_NCI_NDD_NF
ROL r16/32/64, m16/32/64, CL NDD NF optional ROL_GPRv_MEMv_CL_APX_N3EVEX.LLZ.NP.MAP4.SCALABLE D3 /0 ND=1 NF=0/1APX_F + APX_NCI_NDD_NF
ROL r8, r8, imm8 NDD NF optional ROL_GPR8i8_GPR8i8_IMM8_APX_N3EVEX.LLZ.NP.MAP4.WIG C0 /0 ib ND=1 NF=0/1APX_F + APX_NCI_NDD_NF
ROL r8, m8, imm8 NDD NF optional ROL_GPR8i8_MEMi8_IMM8_APX_N3EVEX.LLZ.NP.MAP4.WIG C0 /0 ib ND=1 NF=0/1APX_F + APX_NCI_NDD_NF
ROL r16/32/64, imm8 ROL_GPRv_IMM8_APXEVEX.LLZ.NP.MAP4.SCALABLE C1 /0 ibAPX_F
ROL m16/32/64, imm8 ROL_MEMv_IMM8_APXEVEX.LLZ.NP.MAP4.SCALABLE C1 /0 ibAPX_F
ROL r16/32/64, imm8 NF ROL_GPRv_IMM8_APX_N3EVEX.LLZ.NP.MAP4.SCALABLE C1 /0 ib NF=1APX_F + APX_NCI_NDD_NF
ROL m16/32/64, imm8 NF ROL_MEMv_IMM8_APX_N3EVEX.LLZ.NP.MAP4.SCALABLE C1 /0 ib NF=1APX_F + APX_NCI_NDD_NF

Intrinsics

The C intrinsics of Clang 23.1.2 that compile to ROL, each with the form it compiles to and the Clang options it needs. The forms come from compiling every intrinsic and decoding the result with Intel XED; all intrinsics A–Z explains the method.

IntrinsicCompiles to
_lrotl unsigned long long _lrotl(unsigned long long a, int b)

ROL r16/32/64, CL Legacy

__rolb unsigned char __rolb(unsigned char __X, int __C)

ROL r8, CL Legacy

__rold unsigned int __rold(unsigned int __X, int __C)

ROL r16/32/64, CL Legacy

__rolq unsigned long long __rolq(unsigned long long __X, int __C)

ROL r16/32/64, CL Legacy

__rolw unsigned short __rolw(unsigned short __X, int __C)

ROL r16/32/64, CL Legacy

_rotl unsigned int _rotl(unsigned int a, int b)

ROL r16/32/64, CL Legacy

_rotwl unsigned short _rotwl(unsigned short a, int b)

ROL r16/32/64, CL Legacy

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

CPUID requirements and processors of the XED ISA sets above. Alternatives are separated by “or”; processors follow XED’s chip model, which covers AMD processors up to Zen 2.
ISA setCPUIDProcessors in XED
I186

No CPUID bit: part of the base instruction set.

Every x86-64 processor in XED’s model
I86

No CPUID bit: part of the base instruction set.

Every x86-64 processor in XED’s model
APX_F

APX_F
CPUID.(EAX=07H,ECX=1):EDX[21] APX_F

Nova Lake, Diamond Rapids
APX_F_N3

APX_F + APX_NCI_NDD_NF
CPUID.(EAX=07H,ECX=1):EDX[21] APX_F
CPUID.(EAX=29H,ECX=0):EBX[0] APX_NCI_NDD_NF

Nova Lake, Diamond Rapids

More General-purpose instructions

All 109 General-purpose instructions

More APX instructions

All 88 APX instructions

Sources

  1. Intel XED v2026.08.23 (commit 0bcb6237345c): forms, encodings, ISA sets, CPUID bits and chip model.
  2. Clang's x86 intrinsic headers, LLVM 23.1.2 (commit 85ac56026243): the intrinsics, their signatures and doc comments, and the Clang of that release, which compiled each of them.
  3. Intel 64 and IA-32 Architectures Software Developer's Manual, Volume 2 (325383-092, June 2026)
  4. Intel 64 and IA-32 Architectures Software Developer's Manual, Volume 2 (325383-093, September 2026)
  5. Intel Advanced Performance Extensions (Intel APX) Architecture Specification, revision 7.0 (July 2025)

The tables are derived from Intel XED, Copyright Intel Corporation, licensed under the Apache License 2.0; x86-64.net converted and reformatted them. The intrinsics and their signatures come from Clang, part of the LLVM Project, licensed under the Apache License 2.0 with LLVM Exceptions. The text is our own.