ROR

ROR rotates its operand right: the bits pushed out at the bottom come back in at the top. It is ROL the other way round, and either can stand for the other, since a rotate right by k is a rotate left by the operand’s width minus k. The compilers pick freely: for (x >> 13) | (x << 51) on a uint64_t, GCC 14 at -O2 emits ror rax, 13, Clang 23 rol rax, 51. A rotate of a 16-bit value by 8 in either direction swaps its two bytes.

Count and flags#

The count is masked to 5 bits, or 6 for a 64-bit operand, and an 8- or 16-bit rotate then takes it modulo its width, as the ROL page explains; the C pattern (x >> (n & 31)) | (x << (-n & 31)) compiles to one ror eax, cl. Only CF and OF change: CF receives the bit that landed in the top position, the last one to leave bit 0, and for a count of 1 OF tells whether the top two bits of the result differ. A masked count of 0 changes no flag. Zen 5, rotating a byte by 8 or a word by 16, kept the value and copied its top bit into CF.

RORX#

BMI2 has a rotate right only: RORX takes an immediate count, writes a separate destination and leaves the flags alone. With -march=x86-64-v3, GCC and Clang therefore emit RORX for constant rotates in both directions, a left rotate by 7 of a 32-bit value becoming rorx eax, edi, 25, while rotates by a variable count keep ROL and ROR with CL. AMD’s Zen 5 instruction table lists ROR and RORX alike as single macro-ops with a latency of one cycle.

RCR rotates through CF instead. APX adds forms with a new destination and forms that leave the flags unchanged (NF).

In the optimization guide

What the optimization guide says about ROR, a line per claim. Each links to the claim in the guide, with its sources and where they differ.

Out of order

• Partial register and flag writes: A shift or rotate by CL leaves the flags alone when the count is zero, which is known only when it runs, so it depends on the old flags too.

Forms

Latency and throughput

Operation

What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.

a = dest.read()
n = count & (0x3F if OSIZE == 64 else 0x1F)   # the count is masked,
k = n % OSIZE                    # then taken modulo the operand size
r = low(a >> k | a << (OSIZE - k))
if n != 0 and not nf:            # a count of 0 changes no flag; NF=1
                                 # (APX) none at all
    cf = msb(r)                  # the bit rotated into the top, even
                                 # when k is 0
    flip = msb(r) ^ (r >> (OSIZE - 2) & 1)
    of = flip if n == 1 else UNDEFINED   # the top two bits differ
dest.write(r)                    # even for a count of 0, a 32-bit register
                                 # gets bits 63:32 cleared

a = src.read()
n = count & (0x3F if OSIZE == 64 else 0x1F)   # the count is masked,
k = n % OSIZE                    # then taken modulo the operand size
r = low(a >> k | a << (OSIZE - k))
if n != 0 and not nf:            # a count of 0 changes no flag; NF=1
                                 # none at all
    cf = msb(r)                  # the bit rotated into the top, even
                                 # when k is 0
    flip = msb(r) ^ (r >> (OSIZE - 2) & 1)
    of = flip if n == 1 else UNDEFINED   # the top two bits differ
dest.write(r)                    # the new destination: bits 63:OSIZE
                                 # cleared, even for 8 and 16 bits

Operands

Flags

Exceptions

The exception class is XED's name for the set of exception conditions that a form follows. How to read.

Legacy forms

none in XED

EVEX forms

APX-EVEX-INT

Intrinsics

The C intrinsics of Clang 23.1.2 that compile to ROR, each with the form it compiles to and the Clang options it needs. The forms come from compiling every intrinsic and decoding the result with Intel XED; all intrinsics A–Z explains the method.

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

More General-purpose instructions

• MOVSXD
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• NEG
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• NOT
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• OUT
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• PAUSE
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• POPF
• PUSH
• PUSHA
• PUSHF
• RCL
• RCR
• RET
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All 109 General-purpose instructions

More APX instructions

• MOVDIRI
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• NOT
• OR
• PDEP
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• POPP
• PUSH2
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• PUSHP
• RCL
• RCR
• RDMSR
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• SBB
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• SUB
• TILELOADD
• TILELOADDRS
• TILELOADDRST1
• TILELOADDT1
• TILESTORED
• TZCNT
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All 88 APX instructions