x86-64.net

Instruction

RORX

Rotates the source right by an immediate count into a separate destination without touching the flags.

Extensions
Forms
8 (4 VEX, 4 EVEX)
Data
Intel XED v2026.08.23

RORX rotates its source right by an immediate count and writes the result to a separate register, leaving the flags alone. It is the only rotate of BMI2: there is no RORX with a count in a register, and no left rotate, because a left rotate by k is a right rotate by the width minus k. The ROR page shows the compilers turning constant rotates in both directions into RORX; this page is about what the separate destination buys.

Several rotates of one value

The hash functions of the SHA-2 family mix each word with several rotated copies of itself: SHA-256’s Sigma0 is ror(a, 2) ^ ror(a, 13) ^ ror(a, 22) on 32-bit words (FIPS 180-4). ROR overwrites its operand, so every copy but the last needs a MOV first: GCC 14 and Clang 23 at -O2 with the x86-64 baseline emit two MOVs and three rotates for that line. With -march=x86-64-v3 both emit three RORXs reading EDI and two XORs, and no MOV. SHA-2 in software, for processors without the SHA extension and its SHA256RNDS2, computes such functions in every round.

Swapping halves is a rotate by half the width: (x >> 32) | (x << 32) on a uint64_t becomes rorx rax, rdi, 32.

The count

The immediate is masked to 5 bits, 6 for a 64-bit operand. On Zen 5 a 32-bit RORX by 32 or 64 returned its source unchanged, by 33 or 65 rotated by 1, and a 64-bit RORX by 65 or 129 rotated by 1.

Forms and speed

The source may be in memory; a 32-bit destination has bits 63:32 cleared. APX adds EVEX forms that reach its new registers. AMD’s Zen 5 instruction table lists RORX, like ROR, as one macro-op with a latency of one cycle, three per cycle. RORX belongs to BMI2, part of x86-64-v3.

Forms

Every encoding of RORX that Intel XED knows, one row per XED instruction form (iform). How to read the notation.
InstructionEncodingRequires
RORX r32, r32, imm8 RORX_GPR32d_GPR32d_IMMbVEX.LZ.F2.0F3A.W0 F0 /r ibBMI2
RORX r32, m32, imm8 RORX_GPR32d_MEMd_IMMbVEX.LZ.F2.0F3A.W0 F0 /r ibBMI2
RORX r64, r64, imm8 64-bit mode only RORX_GPR64q_GPR64q_IMMbVEX.LZ.F2.0F3A.W1 F0 /r ibBMI2
RORX r64, m64, imm8 64-bit mode only RORX_GPR64q_MEMq_IMMbVEX.LZ.F2.0F3A.W1 F0 /r ibBMI2
RORX r32, r32, imm8 RORX_GPR32i32_GPR32i32_IMM8_APXEVEX.LLZ.F2.0F3A.W0 F0 /r ibAPX_F + BMI2
RORX r32, m32, imm8 RORX_GPR32i32_MEMi32_IMM8_APXEVEX.LLZ.F2.0F3A.W0 F0 /r ibAPX_F + BMI2
RORX r64, r64, imm8 RORX_GPR64i64_GPR64i64_IMM8_APXEVEX.LLZ.F2.0F3A.W1 F0 /r ibAPX_F + BMI2
RORX r64, m64, imm8 RORX_GPR64i64_MEMi64_IMM8_APXEVEX.LLZ.F2.0F3A.W1 F0 /r ibAPX_F + BMI2

Latency and throughput

What the scheduling models of LLVM 23.1.2 give for each form, not measurements: latency / reciprocal throughput in cycles, the ports under them. A row is a model, or models that agree; a dash, a form that its processors lack. Memory forms: latency from the address, ports without the load and store units. Which processors each model covers.
Modelr32, r32, imm8
r64, r64, imm8		r32, m32, imm8
r64, m64, imm8
Haswell, Broadwell, Skylake, Skylake-SP, Ice Lake, Alder Lake, Sapphire Rapids1 / 0.5p066 / 0.5p06
Lunar Lake1 / 0.33p1356 / 0.33p024
Zen1 / 0.25ALU0 ALU1 ALU2 ALU35 / 0.5ALU0 ALU1 ALU2 ALU3
Zen 21 / 0.25ALU0 ALU1 ALU2 ALU35 / 0.33ALU0 ALU1 ALU2 ALU3
Zen 3, Zen 41 / 0.5ALU1 ALU25 / 0.5ALU1 ALU2

Operation

What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.

a = src.read()
n = imm & (0x3F if OSIZE == 64 else 0x1F)   # the count is masked
dest.write(a >> n | a << (OSIZE - n))   # no flag changes

Run on AMD Zen 5 (EPYC 9645): 30 cases. The APX forms were not run: none of these processors has APX.

Operands

What each form reads and writes, as Intel XED records it: the operands of its syntax, in order, and the implicit ones that the syntax does not name. How to read.
OperandKindAction
RORX r32, r/m32, imm8 RORX r64, r/m64, imm8 64-bit mode only
r32/64explicitwrite
r/m32/64explicitread
imm8explicitread

Flags

None: XED records no flag that the forms test or change.

Exceptions

The exception class is XED's name for the set of exception conditions that a form follows. How to read.

VEX forms
none in XED
EVEX forms
APX-EVEX-BMI

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

CPUID requirements and processors of the XED ISA sets above. Alternatives are separated by “or”; processors follow XED’s chip model, whose AMD processors end with Zen 2, and the CPU data of this site for Zen 3 to Zen 6.
ISA setCPUIDProcessors
BMI2

BMI2
CPUID.(EAX=07H,ECX=0):EBX[8] BMI2

Haswell, Broadwell, Skylake, Comet Lake, Cannon Lake, Ice Lake (client), Tiger Lake, Alder Lake, Arrow Lake, Panther Lake, Nova Lake, Skylake-SP, Cascade Lake, Cooper Lake, Ice Lake (server), Sapphire Rapids, Emerald Rapids, Granite Rapids, Diamond Rapids, Sierra Forest, Clearwater Forest, Knights Landing, Knights Mill, Zen, Zen+, Zen 2, Zen 3, Zen 4, Zen 5, Zen 6
APX_F_BMI2

APX_F + BMI2
CPUID.(EAX=07H,ECX=1):EDX[21] APX_F
CPUID.(EAX=07H,ECX=0):EBX[8] BMI2

Nova Lake, Diamond Rapids

More BMI2 instructions

More APX instructions

All 88 APX instructions

Sources

  1. Intel XED v2026.08.23 (commit 0bcb6237345c): forms, encodings, operands, flags, exception classes, attributes, ISA sets, CPUID bits and chip model.
  2. The CPU data of x86-64.net: Zen 3 to Zen 6, from GCC’s -march feature sets and AMD’s Processor Programming References, which the page of each processor cites.
  3. LLVM 23.1.2's x86 scheduling models (commit 85ac56026243): the latency, reciprocal throughput and ports of each form, as llvm-mca reports them.
  4. Intel 64 and IA-32 Architectures Software Developer's Manual, Volume 2 (325383-093, September 2026): Volume 2B, page 4-582 (RORX)
  5. Intel Advanced Performance Extensions (Intel APX) Architecture Specification, revision 9.0 (355828-009, August 2026)
  6. AMD64 Architecture Programmer's Manual, Volume 3: General-Purpose and System Instructions (24594, rev. 3.39, October 2026)
  7. Software Optimization Guide for the AMD Zen5 Microarchitecture (58455, rev. 1.00, August 2024), Wayback Machine copy of AMD's ZIP
  8. NIST FIPS 180-4: Secure Hash Standard (SHS) (August 2015)

The tables are derived from Intel XED, Copyright Intel Corporation, licensed under the Apache License 2.0; x86-64.net converted and reformatted them. The timings come from LLVM's scheduling models, part of the LLVM Project, licensed under the Apache License 2.0 with LLVM Exceptions. The text is our own.