ROUNDPD instruction (SSE4.1)

ROUNDPD rounds each of two doubles to a whole number, still a double. The immediate works as ROUNDPS describes for singles: bits 1:0 give the direction (nearest, down, up or toward zero), bit 2 takes it from MXCSR instead, and bit 3 keeps the precision exception quiet; ROUNDSD lists which immediate each C function compiles to, the same ones as here. On Zen 5, in a masked case with DAZ set, rounding 1.0000000000000002, the double just above 1.0, down under 1 (bit 3 clear) gave 1.0 and set PE, since the result was inexact; in a masked, clean case, rounding -1.7976931348623157e308 (-DBL_MAX) and 1.0 toward zero under 0Bh left both as they were, already whole numbers, the way ROUNDPS reports values of 2^23 and more unchanged for singles.

Vectorizing the loop

With -msse4.1, GCC 14 and Clang 23 at -O2 compile floor(x) to roundsd xmm0, xmm0, 9, as ROUNDSD’s page shows. Unlike the single-precision loop, which ROUNDPS’s page says GCC vectorizes once -fno-trapping-math allows it, a loop of floor calls over double stayed scalar in GCC’s build either way, and even under -ffast-math; only Clang moved it to ROUNDPD, two doubles at a time, regardless of those options.

AMD’s guide lists ROUNDPD as one macro-op with a latency of three cycles, on pipes FP2 and FP3, as for ROUNDPS. The memory operand must be aligned to 16 bytes, and AVX-512 has no EVEX encoding of it; it rounds with VRNDSCALEPD instead. VROUNDPD is the VEX form, and ROUNDSS the single-precision scalar form.

Forms

Every encoding of ROUNDPD that Intel XED knows, one row per XED instruction form (iform). How to read the notation.

Instruction	Encoding	Requires
`ROUNDPD xmm, m128, imm8` ROUNDPD_XMMpd_MEMpd_IMMb	`66 0F 3A 09 /r ib`	SSE4.1
`ROUNDPD xmm, xmm, imm8` ROUNDPD_XMMpd_XMMpd_IMMb	`66 0F 3A 09 /r ib`	SSE4.1

Data flow

Where the elements of the sources go, element 0 on the right; results that depend on a control value are drawn for an example. How to read.

Element-wise: each double of the result comes from the double in the same place in each source.

Result double i comes from double i of xmm2. Result doubles 1 to 0: r1, r0.

Operation

What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.

for i in range(2):
    xmm1.f64[i] = round(src2.f64[i], imm8)
# imm8[1:0]: rn, rd, ru, rz; bit 2: MXCSR.RC; bit 3: no PE
# bits 128 and up of the register are unchanged

Run on AMD Zen 5 (EPYC 9645): 2 cases.

Operands

What each form reads and writes, as Intel XED records it: the operands of its syntax, in order, and the implicit ones that the syntax does not name. How to read.

Operand	Kind	Action
`ROUNDPD xmm, xmm/m128, imm8`
`xmm`	explicit	write
`xmm/m128`	explicit	read
`imm8`	explicit	read

Flags

None: XED records no flag that the forms test or change.

Exceptions

The exception class is XED's name for the set of exception conditions that a form follows. How to read.

All forms: SSE_TYPE_2

Attributes

What else XED records about the forms. How to read.

All forms: follows MXCSR
Memory forms: aligned memory operand

Intrinsics

The C intrinsics of Clang 23.1.2 that compile to ROUNDPD, each with the form it compiles to and the Clang options it needs. The forms come from compiling every intrinsic and decoding the result with Intel XED; all intrinsics A–Z explains the method.

Intrinsic	Compiles to
`_mm_ceil_pd` `__m128d _mm_ceil_pd(__m128d X)`	`ROUNDPD xmm, xmm, imm8` Legacy -msse4.1
`_mm_floor_pd` `__m128d _mm_floor_pd(__m128d X)`	`ROUNDPD xmm, xmm, imm8` Legacy -msse4.1
`_mm_round_pd` `__m128d _mm_round_pd(__m128d X, const int M)`	`ROUNDPD xmm, xmm, imm8` Legacy -msse4.1

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

CPUID requirements and processors of the XED ISA sets above. Alternatives are separated by “or”; processors follow XED’s chip model, whose AMD processors end with Zen 2, and the CPU data of this site for Zen 3 to Zen 6.

ISA set	CPUID	Processors
`SSE4` SSE4.1	SSE4.1 `CPUID.01H:ECX[19]` SSE4.1	Penryn, Nehalem, Westmere, Sandy Bridge, Ivy Bridge, Haswell, Broadwell, Skylake, Comet Lake, Cannon Lake, Ice Lake (client), Tiger Lake, Alder Lake, Arrow Lake, Panther Lake, Nova Lake, Skylake-SP, Cascade Lake, Cooper Lake, Ice Lake (server), Sapphire Rapids, Emerald Rapids, Granite Rapids, Diamond Rapids, Silvermont, Goldmont, Goldmont Plus, Tremont, Snow Ridge, Lakefield, Sierra Forest, Clearwater Forest, Knights Landing, Knights Mill, K10 (Family 10h), Bulldozer, Piledriver, Zen, Zen+, Zen 2, Zen 3, Zen 4, Zen 5, Zen 6 Note: XED's AMD_K10 inherits everything from its Westmere chip, including SSSE3, SSE4.1, SSE4.2, AES-NI and PCLMULQDQ; GCC's -march=amdfam10 has none of them.

More SSE4.1 instructions

All 49 SSE4.1 instructions

Vectorizing the loop#