ROUNDPS instruction (SSE4.1)

ROUNDPS rounds each of four singles to a whole number and leaves the result a single, so -2.7 becomes -3.0 or -2.0 rather than an integer in a register. The immediate says how:

bits 1:0 pick the direction: to nearest with ties to even (0), down (1), up (2) or toward zero (3);
bit 2 set ignores those two bits and takes the direction from MXCSR.RC instead;
bit 3 set keeps the precision exception quiet, so that a value with a fraction neither sets PE nor faults when PE is unmasked.

Bit 3 does not silence anything else: on Zen 5 an SNaN still set IE, and with IE unmasked it faulted under 0Ch and 0Dh. Results keep their sign, so rounding -0.32 up gave -0.0, and -0.5 to nearest gave -0.0. With DAZ set, a denormal counts as zero: rounding the smallest one up gave 0, not

Both vendors’ manuals say that ROUNDPS never reports a denormal operand. Values of 2^23 and more have no fraction and come back unchanged.

The C library’s rounding functions

Each C function is one immediate. With -msse4.1, GCC 14 and Clang 23 at -O2 compile floorf to 9, ceilf to 0Ah, truncf to 0Bh, roundevenf to 8, nearbyintf to 0Ch and rintf to 4: only rint may report an inexact result, so it alone has bit 3 clear. roundf rounds halves away from zero, which no mode does; Clang adds 0.49999997 (the largest single below 0.5) with the sign of x and truncates, while GCC calls the library.

Clang turns a loop over floorf into ROUNDPS, four elements at a time. GCC keeps it scalar, one ROUNDSS per element, unless -fno-trapping-math is given. Without SSE4.1, Clang calls floorf for each element, and GCC inlines a test that the magnitude is below 2^23, a truncating CVTTSS2SI and the conversion back, with a correction of one.

Its relatives

ROUNDPD rounds doubles, and ROUNDSS and ROUNDSD the low element only. VROUNDPS adds a 256-bit form; AVX-512 has no EVEX encoding of it, and rounds with VRNDSCALEPS, whose immediate also keeps a number of fraction bits. To get an integer in the end, CVTTPS2DQ after ROUNDPS or CVTPS2DQ with MXCSR’s mode does the conversion. The instruction table of AMD’s Zen 5 guide lists ROUNDPS as one macro-op with a latency of three cycles.

Forms

Every encoding of ROUNDPS that Intel XED knows, one row per XED instruction form (iform). How to read the notation.

Instruction	Encoding	Requires
`ROUNDPS xmm, m128, imm8` ROUNDPS_XMMps_MEMps_IMMb	`66 0F 3A 08 /r ib`	SSE4.1
`ROUNDPS xmm, xmm, imm8` ROUNDPS_XMMps_XMMps_IMMb	`66 0F 3A 08 /r ib`	SSE4.1

Data flow

Where the elements of the sources go, element 0 on the right; results that depend on a control value are drawn for an example. How to read.

Element-wise: each single of the result comes from the single in the same place in each source.

Result single i comes from single i of xmm2. Result singles 3 to 0: r3, r2, r1, r0.

Operation

What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.

for i in range(4):
    xmm1.f32[i] = round(src2.f32[i], imm8)
# imm8[1:0]: rn, rd, ru, rz; bit 2: MXCSR.RC; bit 3: no PE
# bits 128 and up of the register are unchanged

Run on AMD Zen 5 (EPYC 9645): 18 cases.

Operands

What each form reads and writes, as Intel XED records it: the operands of its syntax, in order, and the implicit ones that the syntax does not name. How to read.

Operand	Kind	Action
`ROUNDPS xmm, xmm/m128, imm8`
`xmm`	explicit	write
`xmm/m128`	explicit	read
`imm8`	explicit	read

Flags

None: XED records no flag that the forms test or change.

Exceptions

The exception class is XED's name for the set of exception conditions that a form follows. How to read.

All forms: SSE_TYPE_2

Attributes

What else XED records about the forms. How to read.

All forms: follows MXCSR
Memory forms: aligned memory operand

Intrinsics

The C intrinsics of Clang 23.1.2 that compile to ROUNDPS, each with the form it compiles to and the Clang options it needs. The forms come from compiling every intrinsic and decoding the result with Intel XED; all intrinsics A–Z explains the method.

Intrinsic	Compiles to
`_mm_ceil_ps` `__m128 _mm_ceil_ps(__m128 X)`	`ROUNDPS xmm, xmm, imm8` Legacy -msse4.1
`_mm_floor_ps` `__m128 _mm_floor_ps(__m128 X)`	`ROUNDPS xmm, xmm, imm8` Legacy -msse4.1
`_mm_round_ps` `__m128 _mm_round_ps(__m128 X, const int M)`	`ROUNDPS xmm, xmm, imm8` Legacy -msse4.1

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

CPUID requirements and processors of the XED ISA sets above. Alternatives are separated by “or”; processors follow XED’s chip model, whose AMD processors end with Zen 2, and the CPU data of this site for Zen 3 to Zen 6.

ISA set	CPUID	Processors
`SSE4` SSE4.1	SSE4.1 `CPUID.01H:ECX[19]` SSE4.1	Penryn, Nehalem, Westmere, Sandy Bridge, Ivy Bridge, Haswell, Broadwell, Skylake, Comet Lake, Cannon Lake, Ice Lake (client), Tiger Lake, Alder Lake, Arrow Lake, Panther Lake, Nova Lake, Skylake-SP, Cascade Lake, Cooper Lake, Ice Lake (server), Sapphire Rapids, Emerald Rapids, Granite Rapids, Diamond Rapids, Silvermont, Goldmont, Goldmont Plus, Tremont, Snow Ridge, Lakefield, Sierra Forest, Clearwater Forest, Knights Landing, Knights Mill, K10 (Family 10h), Bulldozer, Piledriver, Zen, Zen+, Zen 2, Zen 3, Zen 4, Zen 5, Zen 6 Note: XED's AMD_K10 inherits everything from its Westmere chip, including SSSE3, SSE4.1, SSE4.2, AES-NI and PCLMULQDQ; GCC's -march=amdfam10 has none of them.

More SSE4.1 instructions

All 49 SSE4.1 instructions

The C library’s rounding functions#

Its relatives#