ROUNDSS instruction (SSE4.1)

ROUNDSS rounds the low single of its source to a whole number, still a single, and keeps singles 1 to 3 of the destination. The immediate works as ROUNDPS describes: bits 1:0 give the direction, bit 2 takes MXCSR’s instead, and bit 3 keeps the precision exception quiet. ROUNDSD, the double form, shows which immediate each C function compiles to; the singles use the same ones. On Zen 5:

roundss xmm4, dword ptr [mem], 8 turned 3.0 into 3.0, with singles 1 to 3 taken from the old XMM4, not from memory, which supplies only four bytes;
under 0Dh, which rounds as MXCSR says (to nearest here) without the precision exception, the smallest denormal became +0 with DAZ clear, and neither PE nor DE was set; singles 1 to 3 came from the destination, not from the source register.

Without and with SSE4.1

ROUNDSS came with SSE4.1, which the x86-64 baseline lacks. There, in our builds at -O2, GCC 14 inlines floorf(x) as a test that the magnitude is small enough, a truncating CVTTSS2SI, the conversion back and a correction by one, while Clang 23 calls floorf. With -march=x86-64-v2 both emit roundss xmm0, xmm0, 9, and ceilf, truncf, rintf and nearbyintf become immediates 0Ah, 0Bh, 4 and 0Ch. (int)floorf(x) is ROUNDSS and then CVTTSS2SI.

The fractional part x - floorf(x) shows the merge with the old destination: GCC copies x with MOVAPS and rounds the copy in place, Clang rounds into another register with roundss xmm1, xmm0, 9, and for roundf Clang clears its destination with XORPS before rounding into it. AMD’s guide for Zen 5 lists ROUNDSS among the instructions that skip waiting for the old destination when its upper bits are known to be zero (Section 2.11.5), and its latency spreadsheet gives 3 cycles on pipes FP2 and FP3.

The legacy form keeps bits 255:128 (see mixing SSE and AVX); VROUNDSS is the VEX form, and AVX-512 rounds with VRNDSCALESS.

Forms

Every encoding of ROUNDSS that Intel XED knows, one row per XED instruction form (iform). How to read the notation.

Instruction	Encoding	Requires
`ROUNDSS xmm, m32, imm8` ROUNDSS_XMMd_MEMd_IMMb	`66 0F 3A 0A /r ib`	SSE4.1
`ROUNDSS xmm, xmm, imm8` ROUNDSS_XMMd_XMMd_IMMb	`66 0F 3A 0A /r ib`	SSE4.1

Data flow

Where the elements of the sources go, element 0 on the right; results that depend on a control value are drawn for an example. How to read.

Scalar: only the low single is computed; the other singles come from xmm1.

Result single 0 is computed from single 0 of xmm2; singles 3 to 1 are those of xmm1. Result singles 3 to 0: a3, a2, a1, r0.

Operation

What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.

xmm1.f32[0] = round(src2.f32[0], imm8)
# xmm1.d[1] to [3] keep their values
# imm8[1:0]: rn, rd, ru, rz; bit 2: MXCSR.RC; bit 3: no PE
# bits 128 and up of the register are unchanged

Run on AMD Zen 5 (EPYC 9645): 2 cases.

Operands

What each form reads and writes, as Intel XED records it: the operands of its syntax, in order, and the implicit ones that the syntax does not name. How to read.

Operand	Kind	Action
`ROUNDSS xmm, xmm/m32, imm8`
`xmm`	explicit	read, write
`xmm/m32`	explicit	read
`imm8`	explicit	read

Flags

None: XED records no flag that the forms test or change.

Exceptions

The exception class is XED's name for the set of exception conditions that a form follows. How to read.

All forms: SSE_TYPE_3

Attributes

What else XED records about the forms. How to read.

All forms: follows MXCSR

Intrinsics

The C intrinsics of Clang 23.1.2 that compile to ROUNDSS, each with the form it compiles to and the Clang options it needs. The forms come from compiling every intrinsic and decoding the result with Intel XED; all intrinsics A–Z explains the method.

Intrinsic	Compiles to
`_mm_ceil_ss` `__m128 _mm_ceil_ss(__m128 X, __m128 Y)`	`ROUNDSS xmm, xmm, imm8` Legacy -msse4.1
`_mm_floor_ss` `__m128 _mm_floor_ss(__m128 X, __m128 Y)`	`ROUNDSS xmm, xmm, imm8` Legacy -msse4.1
`_mm_round_ss` `__m128 _mm_round_ss(__m128 X, __m128 Y, const int M)`	`ROUNDSS xmm, xmm, imm8` Legacy -msse4.1

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

CPUID requirements and processors of the XED ISA sets above. Alternatives are separated by “or”; processors follow XED’s chip model, whose AMD processors end with Zen 2, and the CPU data of this site for Zen 3 to Zen 6.

ISA set	CPUID	Processors
`SSE4` SSE4.1	SSE4.1 `CPUID.01H:ECX[19]` SSE4.1	Penryn, Nehalem, Westmere, Sandy Bridge, Ivy Bridge, Haswell, Broadwell, Skylake, Comet Lake, Cannon Lake, Ice Lake (client), Tiger Lake, Alder Lake, Arrow Lake, Panther Lake, Nova Lake, Skylake-SP, Cascade Lake, Cooper Lake, Ice Lake (server), Sapphire Rapids, Emerald Rapids, Granite Rapids, Diamond Rapids, Silvermont, Goldmont, Goldmont Plus, Tremont, Snow Ridge, Lakefield, Sierra Forest, Clearwater Forest, Knights Landing, Knights Mill, K10 (Family 10h), Bulldozer, Piledriver, Zen, Zen+, Zen 2, Zen 3, Zen 4, Zen 5, Zen 6 Note: XED's AMD_K10 inherits everything from its Westmere chip, including SSSE3, SSE4.1, SSE4.2, AES-NI and PCLMULQDQ; GCC's -march=amdfam10 has none of them.

More SSE4.1 instructions

All 49 SSE4.1 instructions

Without and with SSE4.1#