RSQRTPS instruction (SSE)

RSQRTPS estimates 1/sqrt(x) for each of four packed singles, leaving bits 128 and up of the register unchanged. Intel’s manual allows a relative error of up to 1.5 times 2^-12 and does not fix the bits, so the estimate can differ between processors; the Operation section accepts any result within that bound and gives the worst error among Zen 5’s recorded estimates. RSQRTSS describes the special inputs and the Newton-Raphson step that refines the estimate in compiled code, and VRSQRTPS is the VEX and EVEX form. The recorded cases:

with DAZ clear and FTZ clear, in a case with no denormal or overflow involved, 0 and -0 gave +infinity and -infinity, keeping the sign, +infinity gave +0, and -infinity gave the floating-point indefinite, FFC00000h, as any other negative operand does since a negative root is invalid;
with DAZ set and FTZ clear, a case of four denormals, positive and negative, all gave infinity of the matching sign; with DAZ clear and FTZ set instead, a lone denormal did the same;
with DAZ and FTZ both clear, the smallest normal single’s estimate, about 2^63, and the largest normal single’s, about 2^-64, were both recorded within the bound, 1/sqrt(1.0), close to but not exactly 1.0, likewise, and the negative of that largest single gave the indefinite again;
with every exception unmasked, a signaling NaN came back quiet and set no flag.

AMD’s latency spreadsheet for Zen 5 gives RSQRTPS one macro-op with a latency of four cycles, on pipes FP1 and FP2. The memory operand must be aligned to 16 bytes. RCPPS is the reciprocal, and RSQRTSS the scalar form that compilers reach for under -ffast-math.

Forms

Every encoding of RSQRTPS that Intel XED knows, one row per XED instruction form (iform). How to read the notation.

Instruction	Encoding	Requires
`RSQRTPS xmm, m128` RSQRTPS_XMMps_MEMps	`NP 0F 52 /r`	SSE
`RSQRTPS xmm, xmm` RSQRTPS_XMMps_XMMps	`NP 0F 52 /r`	SSE

Data flow

Where the elements of the sources go, element 0 on the right; results that depend on a control value are drawn for an example. How to read.

Element-wise: each single of the result comes from the single in the same place in each source.

Result single i comes from single i of xmm2. Result singles 3 to 0: r3, r2, r1, r0.

Operation

What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.

for i in range(4):
    xmm1.f32[i] = rsqrt(src2.f32[i])
# rsqrt: 1/sqrt(a) within 1.5 * 2^-12; Zen 5's 3
# recorded results: 0.5000 * 2^-12 at most
# a denormal is a zero, whatever MXCSR says; a < 0: the
# indefinite; no flags
# bits 128 and up of the register are unchanged

Run on AMD Zen 5 (EPYC 9645): 6 cases.

Operands

What each form reads and writes, as Intel XED records it: the operands of its syntax, in order, and the implicit ones that the syntax does not name. How to read.

Operand	Kind	Action
`RSQRTPS xmm, xmm/m128`
`xmm`	explicit	write
`xmm/m128`	explicit	read

Flags

None: XED records no flag that the forms test or change.

Exceptions

The exception class is XED's name for the set of exception conditions that a form follows. How to read.

All forms: SSE_TYPE_4

Attributes

What else XED records about the forms. How to read.

Memory forms: aligned memory operand

Intrinsics

The C intrinsics of Clang 23.1.2 that compile to RSQRTPS, each with the form it compiles to and the Clang options it needs. The forms come from compiling every intrinsic and decoding the result with Intel XED; all intrinsics A–Z explains the method.

Intrinsic	Compiles to
`_mm_rsqrt_ps` `__m128 _mm_rsqrt_ps(__m128 __a)`	`RSQRTPS xmm, xmm` Legacy -msse

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

CPUID requirements and processors of the XED ISA sets above. Alternatives are separated by “or”; processors follow XED’s chip model, whose AMD processors end with Zen 2, and the CPU data of this site for Zen 3 to Zen 6.

ISA set	CPUID	Processors
`SSE` SSE	SSE `CPUID.01H:EDX[25]` SSE	Every x86-64 processor in XED’s model and Zen 3 to Zen 6

More SSE instructions

All 65 SSE instructions