RSQRTSS instruction (SSE)

RSQRTSS estimates 1/sqrt(x) for the low single of its source and keeps singles 1 to 3 of the destination. Intel’s manual allows a relative error of up to 1.5 times 2^-12 and does not fix the bits, so the estimate can differ between processors; the Operation section accepts any result within that bound and gives the worst error among Zen 5’s recorded estimates. VRSQRTPS describes the special inputs, negative numbers among them, and the Newton-Raphson step that refines the estimate; VRSQRTSS is the VEX form. On Zen 5:

2.87559869e-38 (011C8FFFh) gave 5.89858961e18 (5EA3B800h), from a register and from memory;
2^127 gave 7.66564817e-20 (1FB50000h), where the exact value, 2^-63.5, is about 7.6665e-20;
denormals counted as zeros and gave +infinity, the largest one with DAZ set and the smallest with DAZ clear;
the signaling NaN 7F812345h came back as the quiet 7FC12345h, with every exception unmasked and no flag set;
singles 1 to 3 kept their values throughout.

Under -ffast-math

In our builds at -O2, GCC 14 and Clang 23 use the estimate only when -ffast-math allows it. Then 1.0f / sqrtf(x) becomes RSQRTSS and one Newton-Raphson step in both: with the estimate r, it computes xr^2 - 3 and multiplies that by -0.5r. A loop that normalizes 3-component vectors, scaling each by 1.0f / sqrtf(x*x + y*y + z*z), gives one RSQRTSS per vector in GCC, and RSQRTPS on four vectors at a time in Clang, with RSQRTSS for the elements left over. With -mrecip as well, GCC computes sqrtf(x) itself as x times the refined estimate, with a CMPNEQSS mask that turns the result for 0 into 0; Clang keeps SQRTSS.

The merge shows in the same code: GCC copies x with MOVAPS and takes the estimate in place, while Clang writes it into another register, and in the leftover loop clears that register with XORPS first, so that the instruction does not wait for its last writer. AMD’s guide for Zen 5 lists RSQRTSS among the instructions whose merge it can skip when the upper bits are known to be zero (Section 2.11.5), and its latency spreadsheet gives it 4 cycles on pipes FP1 and FP2. The legacy form keeps bits 255:128 (see mixing SSE and AVX), and the memory form reads four bytes at any alignment. RCPSS estimates 1/x.

Forms

Every encoding of RSQRTSS that Intel XED knows, one row per XED instruction form (iform). How to read the notation.

Instruction	Encoding	Requires
`RSQRTSS xmm, m32` RSQRTSS_XMMss_MEMss	`F3 0F 52 /r`	SSE
`RSQRTSS xmm, xmm` RSQRTSS_XMMss_XMMss	`F3 0F 52 /r`	SSE

Data flow

Where the elements of the sources go, element 0 on the right; results that depend on a control value are drawn for an example. How to read.

Scalar: only the low single is computed; the other singles come from xmm1.

Result single 0 is computed from single 0 of xmm2; singles 3 to 1 are those of xmm1. Result singles 3 to 0: a3, a2, a1, r0.

Operation

What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.

xmm1.f32[0] = rsqrt(src2.f32[0])
# xmm1.d[1] to [3] keep their values
# rsqrt: 1/sqrt(a) within 1.5 * 2^-12; Zen 5's 3
# recorded results: 1.0595 * 2^-12 at most
# a denormal is a zero, whatever MXCSR says; a < 0: the
# indefinite; no flags
# bits 128 and up of the register are unchanged

Run on AMD Zen 5 (EPYC 9645): 6 cases.

Operands

What each form reads and writes, as Intel XED records it: the operands of its syntax, in order, and the implicit ones that the syntax does not name. How to read.

Operand	Kind	Action
`RSQRTSS xmm, xmm/m32`
`xmm`	explicit	read, write
`xmm/m32`	explicit	read

Flags

None: XED records no flag that the forms test or change.

Exceptions

The exception class is XED's name for the set of exception conditions that a form follows. How to read.

All forms: SSE_TYPE_5

Intrinsics

The C intrinsics of Clang 23.1.2 that compile to RSQRTSS, each with the form it compiles to and the Clang options it needs. The forms come from compiling every intrinsic and decoding the result with Intel XED; all intrinsics A–Z explains the method.

Intrinsic	Compiles to
`_mm_rsqrt_ss` `__m128 _mm_rsqrt_ss(__m128 __a)`	`RSQRTSS xmm, xmm` Legacy -msse

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

CPUID requirements and processors of the XED ISA sets above. Alternatives are separated by “or”; processors follow XED’s chip model, whose AMD processors end with Zen 2, and the CPU data of this site for Zen 3 to Zen 6.

ISA set	CPUID	Processors
`SSE` SSE	SSE `CPUID.01H:EDX[25]` SSE	Every x86-64 processor in XED’s model and Zen 3 to Zen 6

More SSE instructions

All 65 SSE instructions

Under -ffast-math#