SAHF instruction (LAHF-SAHF)

SAHF loads five flags from AH: bit 7 into SF, 6 into ZF, 4 into AF, 2 into PF and 0 into CF. Bits 5, 3 and 1 of AH are ignored, and every other flag keeps its value, OF included. It is the reverse of LAHF, which describes saving the arithmetic flags in a register and the CPUID bit that both need in 64-bit mode; this page looks at SAHF’s own use, putting values into the flags.

After an x87 compare

The x87 compares report in the condition codes C3, C2 and C0 of the status word. After FNSTSW AX they sit in bits 6, 2 and 0 of AH, so SAHF turns them into ZF, PF and CF, and the unsigned conditions (JA, JB, SETA …) then read the result as they would after FCOMI. An unordered result, a NaN on either side, sets all three, which makes equality a two-flag test. GCC 14 and Clang 23 at -O2 with -m32 -march=i486 compiled a == b on doubles both ways:

Clang: FUCOMPP, fnstsw ax, SAHF, then SETNP and SETE ANDed, since ZF alone is also set by a NaN.
GCC: no SAHF; and ah, 69 keeps C3, C2 and C0 (45h), and cmp ah, 64 asks for C3 alone.

Setting flags from a value

SAHF puts a computed pattern into CF, ZF, SF, PF and AF at once, and the instruction table of AMD’s Zen 5 guide lists it as one macro-op, while POPF, which can set them too, is microcoded and also loads TF, DF and, depending on privilege, other system flags. What SAHF cannot reach is OF in bit 11; LAHF’s page shows how to restore it with an ADD. Zen 5 recorded both halves of that rule: with AH = 0 all five flags cleared, and OF, set before, stayed set.

Encoding

SAHF is the single byte 9E, without operands. In 64-bit mode it raises #UD on a processor that lacks the LAHF-SAHF bit, CPUID 80000001H ECX[0]; Zen 5 has it, and the bit is part of x86-64-v2.

Forms

Every encoding of SAHF that Intel XED knows, one row per XED instruction form (iform). How to read the notation.

Instruction	Encoding	Requires
`SAHF` SAHF	`9E`	LAHF

Latency and throughput

What the scheduling models of LLVM 23.1.2 give for each form, not measurements: latency / reciprocal throughput in cycles, the ports under them. A row is a model, or models that agree; a dash, a form that its processors lack. Memory forms: latency from the address, ports without the load and store units. Which processors each model covers.

Model	`SAHF`
Sandy Bridge	1 / 0.5p05
Haswell, Broadwell, Skylake, Skylake-SP, Ice Lake	1 / 0.5p06
Alder Lake, Sapphire Rapids	4 / 1p06
Lunar Lake	4 / 0.67p024
Bonnell	2 / 1p01
Silvermont	1 / 0.5IEC0 IEC1
Piledriver	2 / 1EX0 EX1
Zen, Zen 2	2 / 0.25ALU0 ALU1 ALU2 ALU3
Zen 3, Zen 4	1 / 1ALU3
Jaguar	1 / 0.5ALU0 ALU1

Operation

What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.

sf = ah >> 7 & 1
zf = ah >> 6 & 1
af = ah >> 4 & 1
pf = ah >> 2 & 1
cf = ah & 1                      # AH's bits 5, 3 and 1 are ignored; OF stays
# in 64-bit mode, only on a processor with CPUID.80000001H:ECX[0]
# (LAHF-SAHF); #UD otherwise

Run on AMD Zen 5 (EPYC 9645): 8 cases.

Operands

What each form reads and writes, as Intel XED records it: the operands of its syntax, in order, and the implicit ones that the syntax does not name. How to read.

Operand	Kind	Action
`SAHF`
`AH`	implicit	read
`RFLAGS`	implicit	write

Flags

A loaded from AH; blank: not affected. How to read.

SF	ZF	AF	PF	CF
All forms
A	A	A	A	A

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

CPUID requirements and processors of the XED ISA sets above. Alternatives are separated by “or”; processors follow XED’s chip model, whose AMD processors end with Zen 2, and the CPU data of this site for Zen 3 to Zen 6.

ISA set	CPUID	Processors
`LAHF` LAHF-SAHF	LAHF `CPUID.80000001H:ECX[0]` LAHF	Every x86-64 processor in XED’s model and Zen 3 to Zen 6

More LAHF-SAHF instructions

LAHF

After an x87 compare#

Setting flags from a value#

Encoding#