x86-64.net

Instruction

SALC

Sets AL to FFh if the carry flag is set and to 00h if not, like SBB AL, AL but without changing the flags; not in 64-bit mode.

Extensions
Forms
1 (1 Legacy)
Data
Intel XED v2026.08.23

SALC, the one byte D6, sets AL to FFh when CF is 1 and to 00h when CF is 0, and changes no flag. The result is that of sbb al, al, which subtracts AL and the carry from AL, except that SBB also writes the status flags. It exists only outside 64-bit mode; there the same byte is UDB and raises #UD.

Where the manuals list it

AMD’s Volume 2 marks it “undocumented” in its list of instructions that 64-bit mode removes, and its Volume 3 names it only in the appendix tables of instructions that are invalid in 64-bit mode. Intel’s Volume 2 now has an entry for it, which also defines D6 in 64-bit mode as UDB.

In tools

Compilers produce the same mask with a flag-writing SBB instead: in our builds with -m32 at -O2, return a < b ? 0xff : 0; for unsigned a and b becomes CMP and sbb al, al in GCC 14, and CMP and sbb eax, eax after clearing EAX in Clang 23. Neither emits SALC. The assemblers disagree on the name: Clang 23 assembles salc as D6 in 32-bit code, while GNU as 2.44 rejects the mnemonic and objdump 2.44 prints D6 as “(bad)”. Linux 7.3’s KVM emulator handles SALC outside 64-bit mode, setting AL from CF.

The probe that records this site’s Zen 5 cases runs in 64-bit mode, where D6 is UDB, so SALC has no case; UDB’s two cases raised #UD.

Forms

Every encoding of SALC that Intel XED knows, one row per XED instruction form (iform). How to read the notation.
InstructionEncodingRequires
SALC not in 64-bit mode SALCD6Base instruction set

Operation

What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.

al = 0xFF if cf else 0           # no flag changes

Not run on a processor: the instruction does not exist in 64-bit mode, where the probe runs.

Operands

What each form reads and writes, as Intel XED records it: the operands of its syntax, in order, and the implicit ones that the syntax does not name. How to read.
OperandKindAction
SALC not in 64-bit mode
ALimplicitwrite
RFLAGSimplicitread

Flags

T tested; blank: not affected. How to read.
CF
All forms
T

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

CPUID requirements and processors of the XED ISA sets above. Alternatives are separated by “or”; processors follow XED’s chip model, whose AMD processors end with Zen 2, and the CPU data of this site for Zen 3 to Zen 6.
ISA setCPUIDProcessors
I86

No CPUID bit: part of the base instruction set.

Every x86-64 processor in XED’s model and Zen 3 to Zen 6

More General-purpose instructions

All 109 General-purpose instructions

Sources

  1. Intel XED v2026.08.23 (commit 0bcb6237345c): forms, encodings, operands, flags, exception classes, attributes, ISA sets, CPUID bits and chip model.
  2. The CPU data of x86-64.net: Zen 3 to Zen 6, from GCC’s -march feature sets and AMD’s Processor Programming References, which the page of each processor cites.
  3. Intel 64 and IA-32 Architectures Software Developer's Manual, Volume 2 (325383-093, September 2026): Volume 2A, page 3-608 (SALC)
  4. AMD64 Architecture Programmer's Manual, Volume 2: System Programming (24593, rev. 3.46, October 2026)
  5. AMD64 Architecture Programmer's Manual, Volume 3: General-Purpose and System Instructions (24594, rev. 3.39, October 2026)
  6. Linux 7.3: arch/x86/kvm/emulate.c, x86.c and cpuid.c (the instructions KVM emulates after a #UD, and the CPUID bits it offers a guest)

The tables are derived from Intel XED, Copyright Intel Corporation, licensed under the Apache License 2.0; x86-64.net converted and reformatted them. The text is our own.