SAR

SAR shifts its operand right and fills the vacated high bits with copies of the sign bit, so a negative number stays negative. It is the signed counterpart of SHR, which fills with zeros. GCC 14 and Clang 23 at -O2 compile x >> 3 on an int to sar eax, 3, and x >> 31 to a SAR by 31, which gives 0 for a non-negative x and -1 for a negative one: a mask that branch-free code ANDs or XORs with other values.

Rounding down#

A right shift by k divides by 2^k rounding toward minus infinity, while C’s / and IDIV round toward zero: -7 shifted right by 1 is -4, but -7 / 2 is -3. A signed division by a power of two is therefore more than a SAR. Both compilers first add 2^k - 1 to a negative dividend, which makes the shift round up instead:

• x / 2 becomes mov eax, edi, shr eax, 31 (the sign bit, 0 or 1), add eax, edi and sar eax;
• x / 8 becomes lea eax, [rdi + 7], then test edi, edi and cmovns eax, edi to keep the sum only for a negative x, and sar eax, 3.

Where the dividend cannot be negative, or rounding down is what the program wants, as in x >> 3 itself, the SAR alone is the answer.

Count and flags#

The count is masked to 5 bits, or 6 for a 64-bit operand, as for SHL, so a byte shifted by 8 to 31 becomes 0 or -1 depending on its sign. A shift by 1 always clears OF, since the sign cannot change; the note under the flags table says where XED differs. A count of 0 changes no flag, which is why Intel’s optimization manual names shifts as the usual cause of partial flag stalls and recommends a TEST of the result before a SETcc or Jcc that depends on it (Section 3.5.2.5).

SARX from BMI2 takes the count from any register, writes a separate destination and leaves the flags alone; with -march=x86-64-v3, both compilers use it for x >> n. APX adds forms with a new destination and forms that leave the flags unchanged (NF).

In the optimization guide

What the optimization guide says about SAR, a line per claim. Each links to the claim in the guide, with its sources and where they differ.

Out of order

• Partial register and flag writes: A shift or rotate by CL leaves the flags alone when the count is zero, which is known only when it runs, so it depends on the old flags too.

Forms

Latency and throughput

Operation

What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.

s = signed(dest)                 # the value as a signed number
n = count & (0x3F if OSIZE == 64 else 0x1F)   # the count is masked
r = low(s >> n)                  # copies of the sign bit come in
if n != 0 and not nf:            # a count of 0 changes no flag; NF=1
                                 # (APX) none at all
    cf = s >> (n - 1) & 1        # the last bit shifted out: the sign
                                 # bit once n > OSIZE
    of = 0 if n == 1 else UNDEFINED   # the sign never changes
    sf = msb(r)
    zf = r == 0
    pf = parity(r)
    af = UNDEFINED
dest.write(r)                    # even for a count of 0, a 32-bit register
                                 # gets bits 63:32 cleared

s = signed(src)                  # the value as a signed number
n = count & (0x3F if OSIZE == 64 else 0x1F)   # the count is masked
r = low(s >> n)                  # copies of the sign bit come in
if n != 0 and not nf:            # a count of 0 changes no flag; NF=1
                                 # none at all
    cf = s >> (n - 1) & 1        # the last bit shifted out: the sign
                                 # bit once n > OSIZE
    of = 0 if n == 1 else UNDEFINED   # the sign never changes
    sf = msb(r)
    zf = r == 0
    pf = parity(r)
    af = UNDEFINED
dest.write(r)                    # the new destination: bits 63:OSIZE
                                 # cleared, even for 8 and 16 bits

Operands

Flags

Exceptions

The exception class is XED's name for the set of exception conditions that a form follows. How to read.

Legacy forms

none in XED

EVEX forms

APX-EVEX-INT

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

More General-purpose instructions

• MUL
• NEG
• NOP
• NOT
• OR
• OUT
• OUTS
• PAUSE
• POP
• POPA
• POPF
• PUSH
• PUSHA
• PUSHF
• RCL
• RCR
• RET
• ROL
• ROR
• SALC
• SBB
• SCAS
• SETcc
• SHL
• SHLD
• SHR
• SHRD
• STC
• STD
• STI
• STOS
• SUB
• TEST
• UD0
• UD1
• UD2
• UDB
• XADD
• XCHG
• XLAT

All 109 General-purpose instructions

More APX instructions

• MUL
• MULX
• NEG
• NOT
• OR
• PDEP
• PEXT
• POP2
• POP2P
• POPCNT
• POPP
• PUSH2
• PUSH2P
• PUSHP
• RCL
• RCR
• RDMSR
• ROL
• ROR
• RORX
• SARX
• SBB
• SETcc
• SHL
• SHLD
• SHLX
• SHR
• SHRD
• SHRX
• STTILECFG
• SUB
• TILELOADD
• TILELOADDRS
• TILELOADDRST1
• TILELOADDT1
• TILESTORED
• TZCNT
• URDMSR
• UWRMSR
• WRMSRNS

All 88 APX instructions