SARX

SARX shifts its source right arithmetically, copying the sign bit into the vacated bits, by a count taken from any register, and writes the result to a third register without touching the flags. The source may be in memory: sarx eax, [rdi], ecx shifts the doubleword at RDI right by ECX. It does what SAR does with a count in CL, including its rounding toward minus infinity for negative values; SHLX and SHRX are its siblings for the other shifts, and RORX the rotate.

The count#

As with SAR, only the low 5 bits of the count register count, or 6 bits for a 64-bit operand. A count of 32 on a 32-bit operand is therefore a count of 0 and leaves the value as it was, rather than filling it with copies of the sign. C leaves x >> 32 undefined, so compilers rely on the masking: with -march=x86-64-v3, GCC 14 and Clang 23 at -O2 compile both x >> n and x >> (n & 31) on an int to the same single sarx eax, edi, esi.

SARX has no immediate form, so a shift by a constant remains sar rax, 7.

Why without flags#

A shift by CL that happens to be 0 leaves the flags as they were, so the processor must keep the old flags around for it. Intel’s optimization manual says that in Sandy Bridge SHL reg, cl and its kin take three micro-ops, one of which may be dropped only when no later instruction reads the flags (Section 3.5.1.5). SARX has no such link to the flags, needs no move of the count into CL, and keeps its source, so a loop can shift the same value by several counts.

The instruction table of AMD’s Zen 5 guide lists SARX, like SAR, as one macro-op with a latency of one cycle; Intel’s manual places it with the shifts and rotates on the shift units of Golden Cove (Table 2-4).

SARX belongs to BMI2, part of x86-64-v3; APX adds an EVEX form that reaches its new registers.

Forms

Latency and throughput

Operation

What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.

n = count & (0x3F if OSIZE == 64 else 0x1F)   # the count is masked
dest.write(signed(src) >> n)     # copies of the sign bit come in; no flag
                                 # changes, whatever the count

Operands

Flags

None: XED records no flag that the forms test or change.

Exceptions

The exception class is XED's name for the set of exception conditions that a form follows. How to read.

VEX forms

none in XED

EVEX forms

APX-EVEX-BMI

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

More BMI2 instructions

• BZHI
• MULX
• PDEP
• PEXT
• RORX
• SHLX
• SHRX

More APX instructions

• MULX
• NEG
• NOT
• OR
• PDEP
• PEXT
• POP2
• POP2P
• POPCNT
• POPP
• PUSH2
• PUSH2P
• PUSHP
• RCL
• RCR
• RDMSR
• ROL
• ROR
• RORX
• SAR
• SBB
• SETcc
• SHL
• SHLD
• SHLX
• SHR
• SHRD
• SHRX
• STTILECFG
• SUB
• TILELOADD
• TILELOADDRS
• TILELOADDRST1
• TILELOADDT1
• TILESTORED
• TZCNT
• URDMSR
• UWRMSR
• WRMSRNS
• WRSSD

All 88 APX instructions