x86-64.net

Instruction

SBB

Subtracts an integer and the carry flag, the step that chains multi-word subtractions; APX adds a three-operand form.

Extensions
Forms
48 (24 Legacy, 24 EVEX)
Data
Intel XED v2026.08.23

Forms

Every encoding of SBB that Intel XED knows, one row per XED instruction form (iform). How to read the notation.
InstructionEncodingRequires
SBB m8, imm8 SBB_MEMb_IMMb_80r380 /3 ibBase instruction set
SBB r8, imm8 SBB_GPR8_IMMb_80r380 /3 ibBase instruction set
SBB m16/32/64, imm16/32 SBB_MEMv_IMMz81 /3 iw/idBase instruction set
SBB r16/32/64, imm16/32 SBB_GPRv_IMMz81 /3 iw/idBase instruction set
SBB m8, imm8 not in 64-bit mode SBB_MEMb_IMMb_82r382 /3 ibBase instruction set
SBB r8, imm8 not in 64-bit mode SBB_GPR8_IMMb_82r382 /3 ibBase instruction set
SBB m16/32/64, imm8 SBB_MEMv_IMMb83 /3 ibBase instruction set
SBB r16/32/64, imm8 SBB_GPRv_IMMb83 /3 ibBase instruction set
SBB m8, r8 SBB_MEMb_GPR818 /rBase instruction set
SBB r8, r8 SBB_GPR8_GPR8_1818 /rBase instruction set
SBB m16/32/64, r16/32/64 SBB_MEMv_GPRv19 /rBase instruction set
SBB r16/32/64, r16/32/64 SBB_GPRv_GPRv_1919 /rBase instruction set
SBB r8, r8 SBB_GPR8_GPR8_1A1A /rBase instruction set
SBB r8, m8 SBB_GPR8_MEMb1A /rBase instruction set
SBB r16/32/64, r16/32/64 SBB_GPRv_GPRv_1B1B /rBase instruction set
SBB r16/32/64, m16/32/64 SBB_GPRv_MEMv1B /rBase instruction set
SBB AL, imm8 SBB_AL_IMMb1C ibBase instruction set
SBB rAX, imm16/32 SBB_OrAX_IMMz1D iw/idBase instruction set
LOCK SBB m8, imm8 SBB_LOCK_MEMb_IMMb_80r380 /3 ibBase instruction set
LOCK SBB m16/32/64, imm16/32 SBB_LOCK_MEMv_IMMz81 /3 iw/idBase instruction set
LOCK SBB m8, imm8 not in 64-bit mode SBB_LOCK_MEMb_IMMb_82r382 /3 ibBase instruction set
LOCK SBB m16/32/64, imm8 SBB_LOCK_MEMv_IMMb83 /3 ibBase instruction set
LOCK SBB m8, r8 SBB_LOCK_MEMb_GPR818 /rBase instruction set
LOCK SBB m16/32/64, r16/32/64 SBB_LOCK_MEMv_GPRv19 /rBase instruction set
SBB r8, r8 SBB_GPR8i8_GPR8i8_APXEVEX.LLZ.NP.MAP4.WIG 18 /r
EVEX.LLZ.NP.MAP4.WIG 1A /r		APX_F
SBB m8, r8 SBB_MEMi8_GPR8i8_APXEVEX.LLZ.NP.MAP4.WIG 18 /rAPX_F
SBB r16/32/64, r16/32/64, imm8 NDD SBB_GPRv_GPRv_IMM8_APX_N3EVEX.LLZ.NP.MAP4.SCALABLE 83 /3 ib ND=1APX_F + APX_NCI_NDD_NF
SBB r16/32/64, m16/32/64, imm8 NDD SBB_GPRv_MEMv_IMM8_APX_N3EVEX.LLZ.NP.MAP4.SCALABLE 83 /3 ib ND=1APX_F + APX_NCI_NDD_NF
SBB r8, r8, r8 NDD SBB_GPR8i8_GPR8i8_GPR8i8_APX_N3EVEX.LLZ.NP.MAP4.WIG 18 /r ND=1
EVEX.LLZ.NP.MAP4.WIG 1A /r ND=1		APX_F + APX_NCI_NDD_NF
SBB r8, m8, r8 NDD SBB_GPR8i8_MEMi8_GPR8i8_APX_N3EVEX.LLZ.NP.MAP4.WIG 18 /r ND=1APX_F + APX_NCI_NDD_NF
SBB r16/32/64, r16/32/64 SBB_GPRv_GPRv_APXEVEX.LLZ.NP.MAP4.SCALABLE 19 /r
EVEX.LLZ.NP.MAP4.SCALABLE 1B /r		APX_F
SBB m16/32/64, r16/32/64 SBB_MEMv_GPRv_APXEVEX.LLZ.NP.MAP4.SCALABLE 19 /rAPX_F
SBB r16/32/64, r16/32/64, r16/32/64 NDD SBB_GPRv_GPRv_GPRv_APX_N3EVEX.LLZ.NP.MAP4.SCALABLE 19 /r ND=1
EVEX.LLZ.NP.MAP4.SCALABLE 1B /r ND=1		APX_F + APX_NCI_NDD_NF
SBB r16/32/64, m16/32/64, r16/32/64 NDD SBB_GPRv_MEMv_GPRv_APX_N3EVEX.LLZ.NP.MAP4.SCALABLE 19 /r ND=1APX_F + APX_NCI_NDD_NF
SBB r8, m8 SBB_GPR8i8_MEMi8_APXEVEX.LLZ.NP.MAP4.WIG 1A /rAPX_F
SBB r8, r8, m8 NDD SBB_GPR8i8_GPR8i8_MEMi8_APX_N3EVEX.LLZ.NP.MAP4.WIG 1A /r ND=1APX_F + APX_NCI_NDD_NF
SBB r16/32/64, m16/32/64 SBB_GPRv_MEMv_APXEVEX.LLZ.NP.MAP4.SCALABLE 1B /rAPX_F
SBB r8, r8, imm8 NDD SBB_GPR8i8_GPR8i8_IMM8_APX_N3EVEX.LLZ.NP.MAP4.WIG 80 /3 ib ND=1APX_F + APX_NCI_NDD_NF
SBB r8, m8, imm8 NDD SBB_GPR8i8_MEMi8_IMM8_APX_N3EVEX.LLZ.NP.MAP4.WIG 80 /3 ib ND=1APX_F + APX_NCI_NDD_NF
SBB r16/32/64, r16/32/64, m16/32/64 NDD SBB_GPRv_GPRv_MEMv_APX_N3EVEX.LLZ.NP.MAP4.SCALABLE 1B /r ND=1APX_F + APX_NCI_NDD_NF
SBB r8, imm8 SBB_GPR8i8_IMM8_APXEVEX.LLZ.NP.MAP4.WIG 80 /3 ibAPX_F
SBB m8, imm8 SBB_MEMi8_IMM8_APXEVEX.LLZ.NP.MAP4.WIG 80 /3 ibAPX_F
SBB r16/32/64, imm16/32 SBB_GPRv_IMMz_APXEVEX.LLZ.NP.MAP4.SCALABLE 81 /3 iw/idAPX_F
SBB m16/32/64, imm16/32 SBB_MEMv_IMMz_APXEVEX.LLZ.NP.MAP4.SCALABLE 81 /3 iw/idAPX_F
SBB r16/32/64, r16/32/64, imm16/32 NDD SBB_GPRv_GPRv_IMMz_APX_N3EVEX.LLZ.NP.MAP4.SCALABLE 81 /3 iw/id ND=1APX_F + APX_NCI_NDD_NF
SBB r16/32/64, m16/32/64, imm16/32 NDD SBB_GPRv_MEMv_IMMz_APX_N3EVEX.LLZ.NP.MAP4.SCALABLE 81 /3 iw/id ND=1APX_F + APX_NCI_NDD_NF
SBB r16/32/64, imm8 SBB_GPRv_IMM8_APXEVEX.LLZ.NP.MAP4.SCALABLE 83 /3 ibAPX_F
SBB m16/32/64, imm8 SBB_MEMv_IMM8_APXEVEX.LLZ.NP.MAP4.SCALABLE 83 /3 ibAPX_F

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

CPUID requirements and processors of the XED ISA sets above. Alternatives are separated by “or”; processors follow XED’s chip model, which covers AMD processors up to Zen 2.
ISA setCPUIDProcessors in XED
I86

No CPUID bit: part of the base instruction set.

Every x86-64 processor in XED’s model
APX_F

APX_F
CPUID.(EAX=07H,ECX=1):EDX[21] APX_F

Nova Lake, Diamond Rapids
APX_F_N3

APX_F + APX_NCI_NDD_NF
CPUID.(EAX=07H,ECX=1):EDX[21] APX_F
CPUID.(EAX=29H,ECX=0):EBX[0] APX_NCI_NDD_NF

Nova Lake, Diamond Rapids

More General-purpose instructions

All 109 General-purpose instructions

More APX instructions

All 88 APX instructions

Sources

  1. Intel XED v2026.08.23 (commit 0bcb6237345c): forms, encodings, ISA sets, CPUID bits and chip model.
  2. Intel 64 and IA-32 Architectures Software Developer's Manual, Volume 2 (325383-092, June 2026)
  3. Intel 64 and IA-32 Architectures Software Developer's Manual, Volume 2 (325383-093, September 2026)
  4. Intel Advanced Performance Extensions (Intel APX) Architecture Specification, revision 7.0 (July 2025)

The tables are derived from Intel XED, Copyright Intel Corporation, licensed under the Apache License 2.0; x86-64.net converted and reformatted them. The text is our own.