SBB

SBB subtracts its source and CF from its destination, and leaves the borrow out of that subtraction in CF. It is the subtracting counterpart of ADC: to subtract numbers wider than a register, SUB the lowest words and SBB each higher pair. GCC 14 and Clang 23 at -O2 compile an unsigned __int128 subtraction to sub and sbb, and an __int128 negation to xor edx, edx, NEG of the low half and sbb rdx, rsi, where NEG’s CF is the borrow.

A mask from the carry#

SBB of a register from itself computes 0 - CF: all zeros when CF is clear, all ones when it is set, whatever the register held. Code uses it to turn a condition into a mask without a branch:

• -(a < b) on unsigned numbers becomes cmp rdi, rsi and sbb rax, rax, since CMP’s borrow is the comparison.
• x ? -1 : 0 becomes neg edi and sbb eax, eax, since NEG sets CF for every operand but 0.
• a - (b < c) becomes cmp rsi, rdx and sbb rax, 0.

The result of sbb reg, reg does not depend on the register, but the instruction still names it as a source, and here the manuals differ. AMD’s guide for Zen 5 lists sbb reg, reg among its dependency-removal idioms, executed without waiting for the old value (Section 2.9.2); Intel’s Optimization Reference Manual lists only XOR and SUB of a general-purpose register with itself (Section 3.5.1.7). Clang clears the register with xor eax, eax before such an SBB, GCC does not.

AF#

The flags table follows XED, which records AF as undefined after SBB although it records AF as set by the result for SUB and ADC. Both vendors’ manuals define it: revision 093 of Intel’s, in the SBB entry and in Volume 1’s EFLAGS table, and AMD’s, whose SBB entry marks AF as modified. Zen 5 sets AF as SUB does, and the Operation section computes it so; the note under the flags table gives Intel’s references.

In the optimization guide

What the optimization guide says about SBB, a line per claim. Each links to the claim in the guide, with its sources and where they differ.

Out of order

• Zeroing and dependency-breaking idioms: AMD’s cores recognize two more: cmp eax, eax, which takes no cycle, and sbb eax, eax, which turns the carry flag into 0 or all ones in one cycle without waiting for EAX.

Haswell and Broadwell

• What Broadwell changed: A micro-op of Haswell’s reads three inputs only for FMA, so ADC, SBB and CMOV, which read two registers and the flags, are two micro-ops each; Broadwell makes them one, though stores and blends stay at two.

Zen and Zen+

• Integer execution: Register-to-register moves of 32-bit and 64-bit general registers and of XMM registers, and xchg of general registers, take no execution cycle, while a YMM move renames only its lower half and moves the upper one in a pipe. sources differ

Zen 2

• Integer execution: Register-to-register moves of general registers of 32 and 64 bits, xchg of them and moves of whole XMM and YMM registers take no execution cycle, where Zen 1 moves the upper half of a YMM register in a pipe. sources differ

Zen 3

• Integer execution: Register-to-register moves of general registers of 32 and 64 bits, xchg of them and moves of whole XMM and YMM registers take no execution cycle, nor do the zeroing idioms such as xor eax, eax and vpxor, which also break the dependency on the old value; sbb eax, eax depends only on the carry flag, and pcmpeqd xmm0, xmm0 sets all ones without waiting. sources differ

Zen 4

• Integer execution: Register-to-register moves of general registers of 32 and 64 bits, xchg of them and moves of whole vector registers take no execution cycle, nor do the zeroing idioms such as xor eax, eax and vpxor, which also break the dependency on the old value; sbb eax, eax depends only on the carry flag. sources differ

Forms

Latency and throughput

Operation

What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.

a = dest.read()                  # with LOCK: one atomic read-modify-write
b = sext(src)                    # an immediate is sign-extended to OSIZE
c = cf                           # the borrow in
flags = sub_flags(a, b, c)       # AF too, which XED leaves undefined
dest.write(a - b - c)            # a 32-bit register: bits 63:32 cleared

a = src1.read()
b = sext(src2)                   # an immediate is sign-extended to OSIZE
c = cf                           # the borrow in
flags = sub_flags(a, b, c)
dest.write(a - b - c)            # the new destination: bits 63:OSIZE
                                 # cleared, even for 8 and 16 bits

Operands

Flags

Exceptions

The exception class is XED's name for the set of exception conditions that a form follows. How to read.

Legacy forms

none in XED

EVEX forms

APX-EVEX-INT

Attributes

What else XED records about the forms. How to read.

SBB m8, imm8 SBB m8, r8 SBB m16/32/64, imm16/32 SBB m16/32/64, imm8 SBB m16/32/64, r16/32/64

accepts a LOCK prefix

LOCK forms

locked: atomic read-modify-write; accepts XACQUIRE; accepts XRELEASE

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

More General-purpose instructions

• NEG
• NOP
• NOT
• OR
• OUT
• OUTS
• PAUSE
• POP
• POPA
• POPF
• PUSH
• PUSHA
• PUSHF
• RCL
• RCR
• RET
• ROL
• ROR
• SALC
• SAR
• SCAS
• SETcc
• SHL
• SHLD
• SHR
• SHRD
• STC
• STD
• STI
• STOS
• SUB
• TEST
• UD0
• UD1
• UD2
• UDB
• XADD
• XCHG
• XLAT
• XOR

All 109 General-purpose instructions

More APX instructions

• NEG
• NOT
• OR
• PDEP
• PEXT
• POP2
• POP2P
• POPCNT
• POPP
• PUSH2
• PUSH2P
• PUSHP
• RCL
• RCR
• RDMSR
• ROL
• ROR
• RORX
• SAR
• SARX
• SETcc
• SHL
• SHLD
• SHLX
• SHR
• SHRD
• SHRX
• STTILECFG
• SUB
• TILELOADD
• TILELOADDRS
• TILELOADDRST1
• TILELOADDT1
• TILESTORED
• TZCNT
• URDMSR
• UWRMSR
• WRMSRNS
• WRSSD
• WRSSQ

All 88 APX instructions