Instruction
SCAS
Compares AL, AX, EAX or RAX with the element at [RDI], setting the flags as CMP would, and steps RDI; REPNE SCAS searches for a value.
- Extensions
- Mnemonics
- SCAS, SCASB, SCASW, SCASD, SCASQ
- Forms
- 12 (12 Legacy)
- Data
- Intel XED v2026.08.23
Forms
| Instruction | Encoding | Requires |
|---|---|---|
SCASB
SCASB | AE | Base instruction set |
SCASW
SCASW | 66 AF | Base instruction set |
SCASD
SCASD | AF | Base instruction set |
SCASQ 64-bit mode only
SCASQ | REX.W AF | LM |
REPE SCASB
REPE_SCASB | F3 AE | Base instruction set |
REPNE SCASB
REPNE_SCASB | F2 AE | Base instruction set |
REPE SCASW
REPE_SCASW | 66 F3 AF | Base instruction set |
REPNE SCASW
REPNE_SCASW | 66 F2 AF | Base instruction set |
REPE SCASD
REPE_SCASD | F3 AF | Base instruction set |
REPNE SCASD
REPNE_SCASD | F2 AF | Base instruction set |
REPE SCASQ 64-bit mode only
REPE_SCASQ | F3 REX.W AF | LM |
REPNE SCASQ 64-bit mode only
REPNE_SCASQ | F2 REX.W AF | LM |
CPUID and processors
Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.
| ISA set | CPUID | Processors in XED |
|---|---|---|
I86 | No CPUID bit: part of the base instruction set. | Every x86-64 processor in XED’s model |
I386 | No CPUID bit: part of the base instruction set. | Every x86-64 processor in XED’s model |
LONGMODE | LM | Every x86-64 processor in XED’s model |
More General-purpose instructions
Sources
- Intel XED v2026.08.23 (commit
0bcb6237345c): forms, encodings, ISA sets, CPUID bits and chip model. - Intel 64 and IA-32 Architectures Software Developer's Manual, Volume 2 (325383-092, June 2026)
- Intel 64 and IA-32 Architectures Software Developer's Manual, Volume 2 (325383-093, September 2026)
The tables are derived from Intel XED, Copyright Intel Corporation, licensed under the Apache License 2.0; x86-64.net converted and reformatted them. The text is our own.