Extensions
Mnemonics
SCAS, SCASB, SCASW, SCASD, SCASQ
Forms
12 (12 Legacy)
Data
Intel XED v2026.08.23

Forms

Every encoding of SCAS that Intel XED knows, one row per XED instruction form (iform). How to read the notation.
InstructionEncodingRequires
SCASB SCASBAEBase instruction set
SCASW SCASW66 AFBase instruction set
SCASD SCASDAFBase instruction set
SCASQ 64-bit mode only SCASQREX.W AFLM
REPE SCASB REPE_SCASBF3 AEBase instruction set
REPNE SCASB REPNE_SCASBF2 AEBase instruction set
REPE SCASW REPE_SCASW66 F3 AFBase instruction set
REPNE SCASW REPNE_SCASW66 F2 AFBase instruction set
REPE SCASD REPE_SCASDF3 AFBase instruction set
REPNE SCASD REPNE_SCASDF2 AFBase instruction set
REPE SCASQ 64-bit mode only REPE_SCASQF3 REX.W AFLM
REPNE SCASQ 64-bit mode only REPNE_SCASQF2 REX.W AFLM

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

CPUID requirements and processors of the XED ISA sets above. Alternatives are separated by “or”; processors follow XED’s chip model, which covers AMD processors up to Zen 2.
ISA setCPUIDProcessors in XED
I86

No CPUID bit: part of the base instruction set.

Every x86-64 processor in XED’s model
I386

No CPUID bit: part of the base instruction set.

Every x86-64 processor in XED’s model
LONGMODE

LM
CPUID.80000001H:EDX[29] LM

Every x86-64 processor in XED’s model

More General-purpose instructions

All 109 General-purpose instructions

Sources

  1. Intel XED v2026.08.23 (commit 0bcb6237345c): forms, encodings, ISA sets, CPUID bits and chip model.
  2. Intel 64 and IA-32 Architectures Software Developer's Manual, Volume 2 (325383-092, June 2026)
  3. Intel 64 and IA-32 Architectures Software Developer's Manual, Volume 2 (325383-093, September 2026)

The tables are derived from Intel XED, Copyright Intel Corporation, licensed under the Apache License 2.0; x86-64.net converted and reformatted them. The text is our own.