SEAMOPS instruction (TDX)

Forms

Every encoding of SEAMOPS that Intel XED knows, one row per XED instruction form (iform). How to read the notation.

Instruction	Encoding	Requires
`SEAMOPS` 64-bit mode only SEAMOPS	`66 0F 01 CE`	Base instruction set

Latency and throughput

What the scheduling models of LLVM 23.1.2 give for each form, not measurements: latency / reciprocal throughput in cycles, the ports under them. A row is a model, or models that agree; a dash, a form that its processors lack. Memory forms: latency from the address, ports without the load and store units. Which processors each model covers.

Model	`SEAMOPS`
Sapphire Rapids	100 / 0.25p0156

Operation

What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.

if not seam or vmx_nonroot:
    fault(UD)                    # outside SEAM root operation
if CPL > 0:
    fault(GP, 0)
n = rax                          # the leaf
caps = seamops_capabilities()
if n > 63 or not caps >> n & 1:
    fault(GP, 0)                 # a leaf the processor lacks
if n == 0:
    rax = caps                   # CAPABILITIES
elif n in (7, 8, 9, 10):
    leaf_function(n)             # TDSTATE_ENUM, TDSTATE_LOAD,
                                 # TDSTATE_SAVE_CLEAR and
                                 # UPDATESVNREPORTKEY: no flags
else:
    e = leaf_function(n)         # the others report in RAX, 0 for
    rax = e                      # success, and in ZF
    zf = e != 0
    cf = of = sf = pf = af = 0

Run on AMD Zen 5 (EPYC 9645): 2 cases. Every one raised an exception, at CPL 3, where the probe runs.

Operands

What each form reads and writes, as Intel XED records it: the operands of its syntax, in order, and the implicit ones that the syntax does not name. How to read.

Operand	Kind	Action
`SEAMOPS` 64-bit mode only
`RAX`	implicit	read, write
`RFLAGS`	implicit	write

Flags

M modified, 0 cleared; blank: not affected. How to read.

OF	SF	ZF	AF	PF	CF
All forms
0	0	M	0	0	M

Attributes

What else XED records about the forms. How to read.

All forms: privileged: CPL 0 only; may abort a TSX transaction

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

CPUID requirements and processors of the XED ISA sets above. Alternatives are separated by “or”; processors follow XED’s chip model, whose AMD processors end with Zen 2, and the CPU data of this site for Zen 3 to Zen 6.

ISA set	CPUID	Processors
`TDX` TDX	No CPUID bit: processors with SEAM report its range register (SEAMRR) in bit 15 of the IA32_MTRRCAP MSR, and the TDX module has to be loaded.	Emerald Rapids, Granite Rapids, Diamond Rapids

SEAMOPS