SETcc

SETcc writes 1 to a byte register or a byte of memory when a condition on the flags holds, and 0 when it does not, which turns a comparison into a value. GCC 14 and Clang 23 at -O2 compile return a < b; on two ints to xor eax, eax, cmp edi, esi and setl al. The condition codes are those of Jcc and CMOVcc, and the CMP page shows which to use for signed and unsigned comparisons.

Why the XOR comes first#

SETcc writes only its byte and leaves the rest of the register alone, while the int result needs zeros above it. Clearing EAX beforehand makes the SETcc complete it, and the old contents no longer matter. The XOR has to precede the CMP, since it changes the flags itself. Where no register can be cleared in advance, a MOVZX follows instead: GCC compiles memcmp(a, b, 16) == 0 to two XORs of quadwords, an OR, sete al and movzx eax, al. For a function that returns bool, both compilers leave out the XOR and set only AL.

Other uses#

• Overflow. __builtin_add_overflow on two longs becomes an ADD, a store of the sum and seto al.
• Counting. GCC’s loop that counts the elements equal to k runs xor ecx, ecx, the CMP, sete cl and an ADD to the total each round, with no branch but the loop’s own.
• Choosing a constant. a < b ? 7 : 3 becomes setl al and lea eax, [4*rax + 3]. Intel’s optimization manual recommends SETcc and CMOVcc only for branches that are hard to predict (Section 3.4.1.1, Coding Rule 2).
• Floating point. UCOMISD sets ZF, PF and CF, all three when a NaN makes the operands unordered, so a == b on doubles has to look at PF as well: GCC emits setnp al and a CMOVNE that clears the result unless ZF is set. Clang uses CMPSD instead.

APX#

APX adds SETcc.ZU, an EVEX form that writes 0 or 1 to all 64 bits of its register, so that no XOR has to come first; with a memory operand it still writes one byte. The legacy form stays a byte write.

In the optimization guide

What the optimization guide says about SETcc, a line per claim. Each links to the claim in the guide, with its sources and where they differ.

Out of order

• Partial register and flag writes: setcc writes a single byte, so making a 32-bit 0 or 1 of a condition takes either a movzx after it or a zeroing idiom before.

Branches

• CMOV and branchless code: CMOVcc and SETcc replace a branch with a data dependence: nothing can be mispredicted, but the result waits for the condition and for both inputs, and the core can no longer run ahead on a guessed path.
• CMOV and branchless code: Without CMOV a choice between two constants can be made from the flags with arithmetic: setcc gives 0 or 1, subtracting 1 turns it into a mask of all ones or zeros, and an and with the difference of the constants and an add of one of them gives the result.

Forms

Latency and throughput

Operation

What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.

dest.write(cond(CC))             # 1 or 0, one byte: a register keeps its
                                 # other bits

dest.write(cond(CC))             # SETcc.zu: a register is written whole,
                                 # bits 63:8 cleared; memory is one byte
                                 # all the same

Operands

Flags

Exceptions

The exception class is XED's name for the set of exception conditions that a form follows. How to read.

Legacy forms

none in XED

EVEX forms

APX-EVEX-INT

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

More General-purpose instructions

• NEG
• NOP
• NOT
• OR
• OUT
• OUTS
• PAUSE
• POP
• POPA
• POPF
• PUSH
• PUSHA
• PUSHF
• RCL
• RCR
• RET
• ROL
• ROR
• SALC
• SAR
• SBB
• SCAS
• SHL
• SHLD
• SHR
• SHRD
• STC
• STD
• STI
• STOS
• SUB
• TEST
• UD0
• UD1
• UD2
• UDB
• XADD
• XCHG
• XLAT
• XOR

All 109 General-purpose instructions

More APX instructions

• NOT
• OR
• PDEP
• PEXT
• POP2
• POP2P
• POPCNT
• POPP
• PUSH2
• PUSH2P
• PUSHP
• RCL
• RCR
• RDMSR
• ROL
• ROR
• RORX
• SAR
• SARX
• SBB
• SHL
• SHLD
• SHLX
• SHR
• SHRD
• SHRX
• STTILECFG
• SUB
• TILELOADD
• TILELOADDRS
• TILELOADDRST1
• TILELOADDT1
• TILESTORED
• TZCNT
• URDMSR
• UWRMSR
• WRMSRNS
• WRSSD
• WRSSQ
• WRUSSD

All 88 APX instructions