Instruction
SETcc
Writes 1 or 0 to a byte depending on a condition on the flags; APX adds a form that also clears the rest of the destination register.
- Extensions
- Mnemonics
- SETO, SETNO, SETB, SETC, SETNAE, SETNB, SETNC, SETAE, SETZ, SETE, SETNZ, SETNE, SETBE, SETNA, SETNBE, SETA, SETS, SETNS, SETP, SETPE, SETNP, SETPO, SETL, SETNGE, SETNL, SETGE, SETLE, SETNG, SETNLE, SETG
- Forms
- 6 (2 Legacy, 4 EVEX)
- Data
- Intel XED v2026.08.23
Forms
| Instruction | Encoding | Requires |
|---|---|---|
SETcc m8
SETcc_MEMb | 0F 90+cc /r | Base instruction set |
SETcc r8
SETcc_GPR8 | 0F 90+cc /r | Base instruction set |
SETcc r8
SETcc_GPR8i8_APX_N3 | EVEX.LLZ.F2.MAP4.WIG 40+cc /r | APX_F + APX_NCI_NDD_NF |
SETcc m8
SETcc_MEMi8_APX_N3 | EVEX.LLZ.F2.MAP4.WIG 40+cc /r | APX_F + APX_NCI_NDD_NF |
SETcc r8 ZU
SETcc_GPR8i8_APX_N3_ZU | EVEX.LLZ.F2.MAP4.WIG 40+cc /r ND=1 | APX_F + APX_NCI_NDD_NF |
SETcc m8 ZU
SETcc_MEMi8_APX_N3_ZU | EVEX.LLZ.F2.MAP4.WIG 40+cc /r ND=1 | APX_F + APX_NCI_NDD_NF |
CPUID and processors
Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.
| ISA set | CPUID | Processors in XED |
|---|---|---|
I386 | No CPUID bit: part of the base instruction set. | Every x86-64 processor in XED’s model |
APX_F_N3 | APX_F + APX_NCI_NDD_NF | Nova Lake, Diamond Rapids |
More General-purpose instructions
- NEG
- NOP
- NOT
- OR
- OUT
- OUTS
- PAUSE
- POP
- POPA
- POPF
- PUSH
- PUSHA
- PUSHF
- RCL
- RCR
- RET
- ROL
- ROR
- SALC
- SAR
- SBB
- SCAS
- SHL
- SHLD
- SHR
- SHRD
- STC
- STD
- STI
- STOS
- SUB
- TEST
- UD0
- UD1
- UD2
- UDB
- XADD
- XCHG
- XLAT
- XOR
All 109 General-purpose instructions
More APX instructions
Sources
- Intel XED v2026.08.23 (commit
0bcb6237345c): forms, encodings, ISA sets, CPUID bits and chip model. - Intel 64 and IA-32 Architectures Software Developer's Manual, Volume 2 (325383-092, June 2026)
- Intel 64 and IA-32 Architectures Software Developer's Manual, Volume 2 (325383-093, September 2026)
- Intel Advanced Performance Extensions (Intel APX) Architecture Specification, revision 7.0 (July 2025)
The tables are derived from Intel XED, Copyright Intel Corporation, licensed under the Apache License 2.0; x86-64.net converted and reformatted them. The text is our own.