x86-64.net

Instruction

SHL

Shifts an operand left, filling with zeros (SAL is the same instruction); APX adds three-operand forms and forms that leave the flags unchanged.

Extensions
Mnemonics
SHL, SAL
Forms
60 (24 Legacy, 36 EVEX)
Data
Intel XED v2026.08.23

Forms

Every encoding of SHL that Intel XED knows, one row per XED instruction form (iform). How to read the notation.
InstructionEncodingRequires
SHL m8, imm8 SHL_MEMb_IMMb_C0r4C0 /4 ibBase instruction set
SHL r8, imm8 SHL_GPR8_IMMb_C0r4C0 /4 ibBase instruction set
SHL m8, imm8 SHL_MEMb_IMMb_C0r6C0 /6 ibBase instruction set
SHL r8, imm8 SHL_GPR8_IMMb_C0r6C0 /6 ibBase instruction set
SHL m16/32/64, imm8 SHL_MEMv_IMMb_C1r4C1 /4 ibBase instruction set
SHL r16/32/64, imm8 SHL_GPRv_IMMb_C1r4C1 /4 ibBase instruction set
SHL m16/32/64, imm8 SHL_MEMv_IMMb_C1r6C1 /6 ibBase instruction set
SHL r16/32/64, imm8 SHL_GPRv_IMMb_C1r6C1 /6 ibBase instruction set
SHL m8, imm8 SHL_MEMb_ONE_D0r4D0 /4Base instruction set
SHL r8, imm8 SHL_GPR8_ONE_D0r4D0 /4Base instruction set
SHL m8, imm8 SHL_MEMb_ONE_D0r6D0 /6Base instruction set
SHL r8, imm8 SHL_GPR8_ONE_D0r6D0 /6Base instruction set
SHL m16/32/64, imm8 SHL_MEMv_ONE_D1r6D1 /6Base instruction set
SHL m16/32/64, imm8 SHL_MEMv_ONE_D1r4D1 /4Base instruction set
SHL r16/32/64, imm8 SHL_GPRv_ONE_D1r4D1 /4Base instruction set
SHL r16/32/64, imm8 SHL_GPRv_ONE_D1r6D1 /6Base instruction set
SHL m8, CL SHL_MEMb_CL_D2r4D2 /4Base instruction set
SHL r8, CL SHL_GPR8_CL_D2r4D2 /4Base instruction set
SHL m8, CL SHL_MEMb_CL_D2r6D2 /6Base instruction set
SHL r8, CL SHL_GPR8_CL_D2r6D2 /6Base instruction set
SHL m16/32/64, CL SHL_MEMv_CL_D3r4D3 /4Base instruction set
SHL r16/32/64, CL SHL_GPRv_CL_D3r4D3 /4Base instruction set
SHL m16/32/64, CL SHL_MEMv_CL_D3r6D3 /6Base instruction set
SHL r16/32/64, CL SHL_GPRv_CL_D3r6D3 /6Base instruction set
SHL r8, imm8 SHL_GPR8i8_IMM8_APXEVEX.LLZ.NP.MAP4.WIG C0 /4 ib
EVEX.LLZ.NP.MAP4.WIG C0 /6 ib		APX_F
SHL m8, imm8 SHL_MEMi8_IMM8_APXEVEX.LLZ.NP.MAP4.WIG C0 /4 ib
EVEX.LLZ.NP.MAP4.WIG C0 /6 ib		APX_F
SHL r8, imm8 NF SHL_GPR8i8_IMM8_APX_N3EVEX.LLZ.NP.MAP4.WIG C0 /4 ib NF=1
EVEX.LLZ.NP.MAP4.WIG C0 /6 ib NF=1		APX_F + APX_NCI_NDD_NF
SHL m8, imm8 NF SHL_MEMi8_IMM8_APX_N3EVEX.LLZ.NP.MAP4.WIG C0 /4 ib NF=1
EVEX.LLZ.NP.MAP4.WIG C0 /6 ib NF=1		APX_F + APX_NCI_NDD_NF
SHL r16/32/64, r16/32/64, imm8 NDD NF optional SHL_GPRv_GPRv_ONE_APX_N3EVEX.LLZ.NP.MAP4.SCALABLE D1 /6 ND=1 NF=0/1
EVEX.LLZ.NP.MAP4.SCALABLE D1 /4 ND=1 NF=0/1		APX_F + APX_NCI_NDD_NF
SHL r16/32/64, m16/32/64, imm8 NDD NF optional SHL_GPRv_MEMv_ONE_APX_N3EVEX.LLZ.NP.MAP4.SCALABLE D1 /6 ND=1 NF=0/1
EVEX.LLZ.NP.MAP4.SCALABLE D1 /4 ND=1 NF=0/1		APX_F + APX_NCI_NDD_NF
SHL r8, CL SHL_GPR8i8_CL_APXEVEX.LLZ.NP.MAP4.WIG D2 /4
EVEX.LLZ.NP.MAP4.WIG D2 /6		APX_F
SHL m8, CL SHL_MEMi8_CL_APXEVEX.LLZ.NP.MAP4.WIG D2 /4
EVEX.LLZ.NP.MAP4.WIG D2 /6		APX_F
SHL r8, CL NF SHL_GPR8i8_CL_APX_N3EVEX.LLZ.NP.MAP4.WIG D2 /4 NF=1
EVEX.LLZ.NP.MAP4.WIG D2 /6 NF=1		APX_F + APX_NCI_NDD_NF
SHL m8, CL NF SHL_MEMi8_CL_APX_N3EVEX.LLZ.NP.MAP4.WIG D2 /4 NF=1
EVEX.LLZ.NP.MAP4.WIG D2 /6 NF=1		APX_F + APX_NCI_NDD_NF
SHL r8, r8, CL NDD NF optional SHL_GPR8i8_GPR8i8_CL_APX_N3EVEX.LLZ.NP.MAP4.WIG D2 /4 ND=1 NF=0/1
EVEX.LLZ.NP.MAP4.WIG D2 /6 ND=1 NF=0/1		APX_F + APX_NCI_NDD_NF
SHL r8, m8, CL NDD NF optional SHL_GPR8i8_MEMi8_CL_APX_N3EVEX.LLZ.NP.MAP4.WIG D2 /4 ND=1 NF=0/1
EVEX.LLZ.NP.MAP4.WIG D2 /6 ND=1 NF=0/1		APX_F + APX_NCI_NDD_NF
SHL r16/32/64, CL SHL_GPRv_CL_APXEVEX.LLZ.NP.MAP4.SCALABLE D3 /4
EVEX.LLZ.NP.MAP4.SCALABLE D3 /6		APX_F
SHL m16/32/64, CL SHL_MEMv_CL_APXEVEX.LLZ.NP.MAP4.SCALABLE D3 /4
EVEX.LLZ.NP.MAP4.SCALABLE D3 /6		APX_F
SHL r16/32/64, CL NF SHL_GPRv_CL_APX_N3EVEX.LLZ.NP.MAP4.SCALABLE D3 /4 NF=1
EVEX.LLZ.NP.MAP4.SCALABLE D3 /6 NF=1		APX_F + APX_NCI_NDD_NF
SHL m16/32/64, CL NF SHL_MEMv_CL_APX_N3EVEX.LLZ.NP.MAP4.SCALABLE D3 /4 NF=1
EVEX.LLZ.NP.MAP4.SCALABLE D3 /6 NF=1		APX_F + APX_NCI_NDD_NF
SHL r8, imm8 SHL_GPR8i8_ONE_APXEVEX.LLZ.NP.MAP4.WIG D0 /6
EVEX.LLZ.NP.MAP4.WIG D0 /4		APX_F
SHL m8, imm8 SHL_MEMi8_ONE_APXEVEX.LLZ.NP.MAP4.WIG D0 /6
EVEX.LLZ.NP.MAP4.WIG D0 /4		APX_F
SHL r8, imm8 NF SHL_GPR8i8_ONE_APX_N3EVEX.LLZ.NP.MAP4.WIG D0 /6 NF=1
EVEX.LLZ.NP.MAP4.WIG D0 /4 NF=1		APX_F + APX_NCI_NDD_NF
SHL m8, imm8 NF SHL_MEMi8_ONE_APX_N3EVEX.LLZ.NP.MAP4.WIG D0 /6 NF=1
EVEX.LLZ.NP.MAP4.WIG D0 /4 NF=1		APX_F + APX_NCI_NDD_NF
SHL r16/32/64, r16/32/64, CL NDD NF optional SHL_GPRv_GPRv_CL_APX_N3EVEX.LLZ.NP.MAP4.SCALABLE D3 /4 ND=1 NF=0/1
EVEX.LLZ.NP.MAP4.SCALABLE D3 /6 ND=1 NF=0/1		APX_F + APX_NCI_NDD_NF
SHL r16/32/64, m16/32/64, CL NDD NF optional SHL_GPRv_MEMv_CL_APX_N3EVEX.LLZ.NP.MAP4.SCALABLE D3 /4 ND=1 NF=0/1
EVEX.LLZ.NP.MAP4.SCALABLE D3 /6 ND=1 NF=0/1		APX_F + APX_NCI_NDD_NF
SHL r8, r8, imm8 NDD NF optional SHL_GPR8i8_GPR8i8_IMM8_APX_N3EVEX.LLZ.NP.MAP4.WIG C0 /4 ib ND=1 NF=0/1
EVEX.LLZ.NP.MAP4.WIG C0 /6 ib ND=1 NF=0/1		APX_F + APX_NCI_NDD_NF
SHL r8, m8, imm8 NDD NF optional SHL_GPR8i8_MEMi8_IMM8_APX_N3EVEX.LLZ.NP.MAP4.WIG C0 /4 ib ND=1 NF=0/1
EVEX.LLZ.NP.MAP4.WIG C0 /6 ib ND=1 NF=0/1		APX_F + APX_NCI_NDD_NF
SHL r16/32/64, imm8 SHL_GPRv_IMM8_APXEVEX.LLZ.NP.MAP4.SCALABLE C1 /4 ib
EVEX.LLZ.NP.MAP4.SCALABLE C1 /6 ib		APX_F
SHL m16/32/64, imm8 SHL_MEMv_IMM8_APXEVEX.LLZ.NP.MAP4.SCALABLE C1 /4 ib
EVEX.LLZ.NP.MAP4.SCALABLE C1 /6 ib		APX_F
SHL r16/32/64, imm8 NF SHL_GPRv_IMM8_APX_N3EVEX.LLZ.NP.MAP4.SCALABLE C1 /4 ib NF=1
EVEX.LLZ.NP.MAP4.SCALABLE C1 /6 ib NF=1		APX_F + APX_NCI_NDD_NF
SHL m16/32/64, imm8 NF SHL_MEMv_IMM8_APX_N3EVEX.LLZ.NP.MAP4.SCALABLE C1 /4 ib NF=1
EVEX.LLZ.NP.MAP4.SCALABLE C1 /6 ib NF=1		APX_F + APX_NCI_NDD_NF
SHL r8, r8, imm8 NDD NF optional SHL_GPR8i8_GPR8i8_ONE_APX_N3EVEX.LLZ.NP.MAP4.WIG D0 /4 ND=1 NF=0/1
EVEX.LLZ.NP.MAP4.WIG D0 /6 ND=1 NF=0/1		APX_F + APX_NCI_NDD_NF
SHL r8, m8, imm8 NDD NF optional SHL_GPR8i8_MEMi8_ONE_APX_N3EVEX.LLZ.NP.MAP4.WIG D0 /4 ND=1 NF=0/1
EVEX.LLZ.NP.MAP4.WIG D0 /6 ND=1 NF=0/1		APX_F + APX_NCI_NDD_NF
SHL r16/32/64, r16/32/64, imm8 NDD NF optional SHL_GPRv_GPRv_IMM8_APX_N3EVEX.LLZ.NP.MAP4.SCALABLE C1 /4 ib ND=1 NF=0/1
EVEX.LLZ.NP.MAP4.SCALABLE C1 /6 ib ND=1 NF=0/1		APX_F + APX_NCI_NDD_NF
SHL r16/32/64, m16/32/64, imm8 NDD NF optional SHL_GPRv_MEMv_IMM8_APX_N3EVEX.LLZ.NP.MAP4.SCALABLE C1 /4 ib ND=1 NF=0/1
EVEX.LLZ.NP.MAP4.SCALABLE C1 /6 ib ND=1 NF=0/1		APX_F + APX_NCI_NDD_NF
SHL r16/32/64, imm8 SHL_GPRv_ONE_APXEVEX.LLZ.NP.MAP4.SCALABLE D1 /4
EVEX.LLZ.NP.MAP4.SCALABLE D1 /6		APX_F
SHL m16/32/64, imm8 SHL_MEMv_ONE_APXEVEX.LLZ.NP.MAP4.SCALABLE D1 /4
EVEX.LLZ.NP.MAP4.SCALABLE D1 /6		APX_F
SHL r16/32/64, imm8 NF SHL_GPRv_ONE_APX_N3EVEX.LLZ.NP.MAP4.SCALABLE D1 /4 NF=1
EVEX.LLZ.NP.MAP4.SCALABLE D1 /6 NF=1		APX_F + APX_NCI_NDD_NF
SHL m16/32/64, imm8 NF SHL_MEMv_ONE_APX_N3EVEX.LLZ.NP.MAP4.SCALABLE D1 /4 NF=1
EVEX.LLZ.NP.MAP4.SCALABLE D1 /6 NF=1		APX_F + APX_NCI_NDD_NF

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

CPUID requirements and processors of the XED ISA sets above. Alternatives are separated by “or”; processors follow XED’s chip model, which covers AMD processors up to Zen 2.
ISA setCPUIDProcessors in XED
I186

No CPUID bit: part of the base instruction set.

Every x86-64 processor in XED’s model
I86

No CPUID bit: part of the base instruction set.

Every x86-64 processor in XED’s model
APX_F

APX_F
CPUID.(EAX=07H,ECX=1):EDX[21] APX_F

Nova Lake, Diamond Rapids
APX_F_N3

APX_F + APX_NCI_NDD_NF
CPUID.(EAX=07H,ECX=1):EDX[21] APX_F
CPUID.(EAX=29H,ECX=0):EBX[0] APX_NCI_NDD_NF

Nova Lake, Diamond Rapids

More General-purpose instructions

All 109 General-purpose instructions

More APX instructions

All 88 APX instructions

Sources

  1. Intel XED v2026.08.23 (commit 0bcb6237345c): forms, encodings, ISA sets, CPUID bits and chip model.
  2. Intel 64 and IA-32 Architectures Software Developer's Manual, Volume 2 (325383-092, June 2026)
  3. Intel 64 and IA-32 Architectures Software Developer's Manual, Volume 2 (325383-093, September 2026)
  4. Intel Advanced Performance Extensions (Intel APX) Architecture Specification, revision 7.0 (July 2025)

The tables are derived from Intel XED, Copyright Intel Corporation, licensed under the Apache License 2.0; x86-64.net converted and reformatted them. The text is our own.