SHL

SHL shifts its operand left and fills the vacated low bits with zeros, multiplying by a power of two modulo the operand’s width. SAL is the same instruction under a second name: a left shift is the same for signed and unsigned numbers, unlike the right shifts SHR and SAR. The count is an immediate, the constant 1 or CL; SHLX from BMI2 takes it from any register, writes a separate destination and leaves the flags alone, and GCC 14 and Clang 23 at -O2 use it for x << n when allowed BMI2.

The count is masked#

The processor uses only the low 5 bits of the count, or the low 6 for a 64-bit operand. So shl eax, cl with CL = 32 leaves EAX and the flags as they were (though, as a 32-bit write, it still clears bits 63:32 of RAX), and with CL = 33 it shifts by 1. C leaves x << n undefined when n is at least the width of x, so compilers emit a plain shift; and since the processor masks anyway, both compile x << (n & 63) for a 64-bit x to a lone shl rax, cl, without the AND (GCC prints it as sal).

For 8- and 16-bit operands the count is still masked to 5 bits, not to the operand’s width, so a byte shifted by 8 to 31 becomes 0. The vector shifts differ again: PSLLD and its kin do not mask their count at all, and turn every element to 0 once the count reaches the element’s width.

The flags after a shift#

CF receives the last bit shifted out, which makes shl by 1 followed by JC a test of the top bit. OF is defined for a count of 1 only, so the flags cannot tell whether a longer shift lost significant bits; the flags table and its note show where Intel’s manual and XED disagree on the details.

The /6 encodings#

Besides /4 in ModRM.reg, XED decodes /6 of the same opcodes (C0, C1, D0 to D3) as SHL and marks those forms undocumented. AMD’s opcode map lists them as SHL/SAL, with a note that tools generally lack them; Intel’s leaves /6 empty. Zen 5 ran every /6 form recorded here exactly as the /4 one. APX adds forms with a new destination and forms that leave the flags unchanged (NF).

In the optimization guide

What the optimization guide says about SHL, a line per claim. Each links to the claim in the guide, with its sources and where they differ.

Out of order

• Partial register and flag writes: A shift or rotate by CL leaves the flags alone when the count is zero, which is known only when it runs, so it depends on the old flags too.

Forms

Latency and throughput

Operation

What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.

a = dest.read()
n = count & (0x3F if OSIZE == 64 else 0x1F)   # the count is masked
r = low(a << n)
if n != 0 and not nf:            # a count of 0 changes no flag; NF=1
                                 # (APX) none at all
    c = (a << n) >> OSIZE & 1    # the last bit shifted out: 0 once
                                 # n > OSIZE
    cf = c
    of = msb(r) ^ c if n == 1 else UNDEFINED
    sf = msb(r)
    zf = r == 0
    pf = parity(r)
    af = UNDEFINED
dest.write(r)                    # even for a count of 0, a 32-bit register
                                 # gets bits 63:32 cleared

a = src.read()
n = count & (0x3F if OSIZE == 64 else 0x1F)   # the count is masked
r = low(a << n)
if n != 0 and not nf:            # a count of 0 changes no flag; NF=1
                                 # none at all
    c = (a << n) >> OSIZE & 1    # the last bit shifted out: 0 once
                                 # n > OSIZE
    cf = c
    of = msb(r) ^ c if n == 1 else UNDEFINED
    sf = msb(r)
    zf = r == 0
    pf = parity(r)
    af = UNDEFINED
dest.write(r)                    # the new destination: bits 63:OSIZE
                                 # cleared, even for 8 and 16 bits

Operands

Flags

Exceptions

The exception class is XED's name for the set of exception conditions that a form follows. How to read.

Legacy forms

none in XED

EVEX forms

APX-EVEX-INT

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

More General-purpose instructions

• NEG
• NOP
• NOT
• OR
• OUT
• OUTS
• PAUSE
• POP
• POPA
• POPF
• PUSH
• PUSHA
• PUSHF
• RCL
• RCR
• RET
• ROL
• ROR
• SALC
• SAR
• SBB
• SCAS
• SETcc
• SHLD
• SHR
• SHRD
• STC
• STD
• STI
• STOS
• SUB
• TEST
• UD0
• UD1
• UD2
• UDB
• XADD
• XCHG
• XLAT
• XOR

All 109 General-purpose instructions

More APX instructions

• OR
• PDEP
• PEXT
• POP2
• POP2P
• POPCNT
• POPP
• PUSH2
• PUSH2P
• PUSHP
• RCL
• RCR
• RDMSR
• ROL
• ROR
• RORX
• SAR
• SARX
• SBB
• SETcc
• SHLD
• SHLX
• SHR
• SHRD
• SHRX
• STTILECFG
• SUB
• TILELOADD
• TILELOADDRS
• TILELOADDRST1
• TILELOADDT1
• TILESTORED
• TZCNT
• URDMSR
• UWRMSR
• WRMSRNS
• WRSSD
• WRSSQ
• WRUSSD
• WRUSSQ

All 88 APX instructions