SHLD

SHLD shifts its destination left and fills the vacated low bits from the top of a second register, as if the two formed one value of twice the width with the destination above. The second register is only read. SHRD is the mirror image: it shifts right and fills the top from the bottom of the second register.

That is the step a wide shift needs. GCC 14 and Clang 23 at -O2 compile x << 5 on an unsigned __int128 to shld rdx, rdi, 5 for the high half and a SHL by 5 for the low one, and take 64 bits from the middle of a 128-bit value, (uint64_t)(x >> 20), with a single shrd rax, rsi, 20. A constant funnel shift such as (hi << 52) | (lo >> 12) becomes shld rax, rsi, 52.

The count#

The count is masked to 5 bits, or 6 for a 64-bit operand, as for SHL. For a 128-bit x << n with n in a register, both compilers therefore run SHLD and SHL by CL on the two halves, then test bit 6 of the count and, when n is 64 or more, use two CMOVs to move the low result into the high half and clear the low half.

A masked count of 0 leaves the destination and the flags alone. So the variable funnel shift (hi << n) | (lo >> (-n & 63)) does not become SHLD: for n = 0 it gives hi | lo, where SHLD would give hi. Both compilers build it from two shifts and an OR instead.

16-bit operands#

With a 16-bit operand, the masked count can reach 31, more than the 16 bits the second register supplies. Intel’s and AMD’s manuals leave the result undefined then, and Intel’s leaves all the flags undefined too. Zen 5 shifted the 48 bits of the destination above two copies of the source, so that the source’s bits came in a second time, and cleared CF.

Speed#

Intel’s optimization manual lists SHLD among the instructions of the one “Slow Int” execution unit of Golden Cove, beside MUL and BSR (Table 2-4). AMD’s Zen 5 guide gives SHLD and SHRD a latency of three cycles (Section 2.10.2), and its instruction table lists them as microcoded. APX adds forms with a new destination and forms that leave the flags unchanged (NF).

In the optimization guide

What the optimization guide says about SHLD, a line per claim. Each links to the claim in the guide, with its sources and where they differ.

Bulldozer to Excavator

• Integer execution: SHLD and SHRD are microcoded, 4 cycles in AMD’s table.

Golden Cove and Raptor Cove

• Integer execution: Port 1 alone runs the slower integer operations: multiplication, PDEP and PEXT, popcnt, bsr, crc32 and the double shifts with an immediate count, which LLVM’s models give a latency of three cycles and one per cycle.

Jaguar and Puma

• Integer execution: SHLD and SHRD are microcoded, six to eight macro-ops in AMD’s spreadsheet, and LLVM treats double shifts as slow on these cores.

Silvermont to Goldmont Plus

• Out-of-order and in-order execution: shld and shrd come from microcode at 64 bits, with a memory destination or a count in cl. sources differ

Skylake to Cooper Lake

• Integer execution: Port 1 alone runs integer multiplication, PDEP and PEXT, popcnt, lzcnt, tzcnt, bsf, bsr and the double shifts, with a latency of three cycles and one a cycle in LLVM’s models, as on Golden Cove.

Zen and Zen+

• Integer execution: SHLD is microcoded, taking four cycles in AMD’s spreadsheet, and LLVM treats double shifts as slow for -march=znver1. sources differ

Zen 2

• Integer execution: SHLD and SHRD are microcoded, and LLVM treats them as slow for -march=znver2, as it stops doing for Zen 3. sources differ

Zen 3

• Integer execution: SHLD and SHRD have a latency of three cycles, and LLVM’s -march=znver3 no longer treats them as slow, as it does for the Zen cores before. sources differ

Zen 4

• Integer execution: SHLD and SHRD have a latency of three cycles. sources differ

Forms

Latency and throughput

Operation

What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.

a = dest.read()
b = src.read()
n = count & (0x3F if OSIZE == 64 else 0x1F)   # the count is masked
if OSIZE == 16 and n > 16:
    # Intel's manual leaves the result and the flags undefined. Zen 5
    # shifts the 48 bits of dest:src:src, so that src comes in
    # again, and clears CF.
    dest.write(UNDEFINED)
    if not nf:
        of = sf = zf = UNDEFINED
        af = pf = cf = UNDEFINED
else:
    x = a << OSIZE | b           # dest above src
    r = low(x << n >> OSIZE)     # the top half: dest, with the top n
                                 # bits of src coming in from below
    if n != 0 and not nf:        # a count of 0 changes no flag; NF=1
                                 # (APX) none at all
        cf = x >> (2 * OSIZE - n) & 1   # the last bit shifted out
        flip = msb(r) ^ msb(a)
        of = flip if n == 1 else UNDEFINED   # the sign changed
        sf = msb(r)
        zf = r == 0
        pf = parity(r)
        af = UNDEFINED
    dest.write(r)                # even for a count of 0, a 32-bit
                                 # register gets bits 63:32 cleared

a = src1.read()
b = src2.read()
n = count & (0x3F if OSIZE == 64 else 0x1F)   # the count is masked
if OSIZE == 16 and n > 16:
    # Intel's manual leaves the result and the flags undefined
    dest.write(UNDEFINED)
    if not nf:
        of = sf = zf = UNDEFINED
        af = pf = cf = UNDEFINED
else:
    x = a << OSIZE | b           # src1 above src2
    r = low(x << n >> OSIZE)     # the top half: src1, with the top n
                                 # bits of src2 coming in from below
    if n != 0 and not nf:        # a count of 0 changes no flag; NF=1
                                 # none at all
        cf = x >> (2 * OSIZE - n) & 1   # the last bit shifted out
        flip = msb(r) ^ msb(a)
        of = flip if n == 1 else UNDEFINED   # the sign changed
        sf = msb(r)
        zf = r == 0
        pf = parity(r)
        af = UNDEFINED
    dest.write(r)                # the new destination: bits 63:OSIZE
                                 # cleared, even for 16 bits

Operands

Flags

Exceptions

The exception class is XED's name for the set of exception conditions that a form follows. How to read.

Legacy forms

none in XED

EVEX forms

APX-EVEX-INT

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

More General-purpose instructions

• NEG
• NOP
• NOT
• OR
• OUT
• OUTS
• PAUSE
• POP
• POPA
• POPF
• PUSH
• PUSHA
• PUSHF
• RCL
• RCR
• RET
• ROL
• ROR
• SALC
• SAR
• SBB
• SCAS
• SETcc
• SHL
• SHR
• SHRD
• STC
• STD
• STI
• STOS
• SUB
• TEST
• UD0
• UD1
• UD2
• UDB
• XADD
• XCHG
• XLAT
• XOR

All 109 General-purpose instructions

More APX instructions

• PDEP
• PEXT
• POP2
• POP2P
• POPCNT
• POPP
• PUSH2
• PUSH2P
• PUSHP
• RCL
• RCR
• RDMSR
• ROL
• ROR
• RORX
• SAR
• SARX
• SBB
• SETcc
• SHL
• SHLX
• SHR
• SHRD
• SHRX
• STTILECFG
• SUB
• TILELOADD
• TILELOADDRS
• TILELOADDRST1
• TILELOADDT1
• TILESTORED
• TZCNT
• URDMSR
• UWRMSR
• WRMSRNS
• WRSSD
• WRSSQ
• WRUSSD
• WRUSSQ
• XOR

All 88 APX instructions