x86-64.net

Instruction

SHLD

Shifts an operand left and fills the vacated bits from a second register; APX adds three-operand forms and forms that leave the flags unchanged.

Extensions
Forms
16 (4 Legacy, 12 EVEX)
Data
Intel XED v2026.08.23

Forms

Every encoding of SHLD that Intel XED knows, one row per XED instruction form (iform). How to read the notation.
InstructionEncodingRequires
SHLD m16/32/64, r16/32/64, imm8 SHLD_MEMv_GPRv_IMMb0F A4 /r ibBase instruction set
SHLD r16/32/64, r16/32/64, imm8 SHLD_GPRv_GPRv_IMMb0F A4 /r ibBase instruction set
SHLD m16/32/64, r16/32/64, CL SHLD_MEMv_GPRv_CL0F A5 /rBase instruction set
SHLD r16/32/64, r16/32/64, CL SHLD_GPRv_GPRv_CL0F A5 /rBase instruction set
SHLD r16/32/64, r16/32/64, imm8 SHLD_GPRv_GPRv_IMM8_APXEVEX.LLZ.NP.MAP4.SCALABLE 24 /r ibAPX_F
SHLD m16/32/64, r16/32/64, imm8 SHLD_MEMv_GPRv_IMM8_APXEVEX.LLZ.NP.MAP4.SCALABLE 24 /r ibAPX_F
SHLD r16/32/64, r16/32/64, imm8 NF SHLD_GPRv_GPRv_IMM8_APX_N3EVEX.LLZ.NP.MAP4.SCALABLE 24 /r ib NF=1APX_F + APX_NCI_NDD_NF
SHLD m16/32/64, r16/32/64, imm8 NF SHLD_MEMv_GPRv_IMM8_APX_N3EVEX.LLZ.NP.MAP4.SCALABLE 24 /r ib NF=1APX_F + APX_NCI_NDD_NF
SHLD r16/32/64, r16/32/64, r16/32/64, imm8 NDD NF optional SHLD_GPRv_GPRv_GPRv_IMM8_APX_N3EVEX.LLZ.NP.MAP4.SCALABLE 24 /r ib ND=1 NF=0/1APX_F + APX_NCI_NDD_NF
SHLD r16/32/64, m16/32/64, r16/32/64, imm8 NDD NF optional SHLD_GPRv_MEMv_GPRv_IMM8_APX_N3EVEX.LLZ.NP.MAP4.SCALABLE 24 /r ib ND=1 NF=0/1APX_F + APX_NCI_NDD_NF
SHLD r16/32/64, r16/32/64, CL SHLD_GPRv_GPRv_CL_APXEVEX.LLZ.NP.MAP4.SCALABLE A5 /rAPX_F
SHLD m16/32/64, r16/32/64, CL SHLD_MEMv_GPRv_CL_APXEVEX.LLZ.NP.MAP4.SCALABLE A5 /rAPX_F
SHLD r16/32/64, r16/32/64, CL NF SHLD_GPRv_GPRv_CL_APX_N3EVEX.LLZ.NP.MAP4.SCALABLE A5 /r NF=1APX_F + APX_NCI_NDD_NF
SHLD m16/32/64, r16/32/64, CL NF SHLD_MEMv_GPRv_CL_APX_N3EVEX.LLZ.NP.MAP4.SCALABLE A5 /r NF=1APX_F + APX_NCI_NDD_NF
SHLD r16/32/64, r16/32/64, r16/32/64, CL NDD NF optional SHLD_GPRv_GPRv_GPRv_CL_APX_N3EVEX.LLZ.NP.MAP4.SCALABLE A5 /r ND=1 NF=0/1APX_F + APX_NCI_NDD_NF
SHLD r16/32/64, m16/32/64, r16/32/64, CL NDD NF optional SHLD_GPRv_MEMv_GPRv_CL_APX_N3EVEX.LLZ.NP.MAP4.SCALABLE A5 /r ND=1 NF=0/1APX_F + APX_NCI_NDD_NF

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

CPUID requirements and processors of the XED ISA sets above. Alternatives are separated by “or”; processors follow XED’s chip model, which covers AMD processors up to Zen 2.
ISA setCPUIDProcessors in XED
I386

No CPUID bit: part of the base instruction set.

Every x86-64 processor in XED’s model
APX_F

APX_F
CPUID.(EAX=07H,ECX=1):EDX[21] APX_F

Nova Lake, Diamond Rapids
APX_F_N3

APX_F + APX_NCI_NDD_NF
CPUID.(EAX=07H,ECX=1):EDX[21] APX_F
CPUID.(EAX=29H,ECX=0):EBX[0] APX_NCI_NDD_NF

Nova Lake, Diamond Rapids

More General-purpose instructions

All 109 General-purpose instructions

More APX instructions

All 88 APX instructions

Sources

  1. Intel XED v2026.08.23 (commit 0bcb6237345c): forms, encodings, ISA sets, CPUID bits and chip model.
  2. Intel 64 and IA-32 Architectures Software Developer's Manual, Volume 2 (325383-092, June 2026)
  3. Intel 64 and IA-32 Architectures Software Developer's Manual, Volume 2 (325383-093, September 2026)
  4. Intel Advanced Performance Extensions (Intel APX) Architecture Specification, revision 7.0 (July 2025)

The tables are derived from Intel XED, Copyright Intel Corporation, licensed under the Apache License 2.0; x86-64.net converted and reformatted them. The text is our own.