SHLX

SHLX shifts its source left by a count from any register, zeros coming in at the bottom, and writes a third register without touching the flags. It is the BMI2 form of SHL, and the third of a set whose other members, SHRX and SARX, explain the masked count and why a shift without flags helps. In Intel syntax the count comes last: shlx eax, edi, esi is EDI « ESI. The count register is encoded in VEX.vvvv, so only the value to shift may be in memory.

One instruction for both signs#

A left shift is the same for signed and unsigned numbers, so where right shifts split into SHRX and SARX, SHLX serves both: with -march=x86-64-v3, GCC 14 and Clang 23 at -O2 compile x << n to shlx eax, edi, esi for an int and for an unsigned alike, and to shlx rax, rdi, rsi for a uint64_t. A shift by a constant stays shl eax, 7 (GCC writes sal), as SHLX has no immediate form.

Building masks#

A single variable bit, 1ULL << n, becomes mov eax, 1 and shlx rax, rax, rdi. A mask of the low n bits, (1u << n) - 1, is SHLX of 1 and a subtraction with GCC, and SHLX of -1 and a NOT with Clang. Both give 0, not all ones, for n = 32: the count is masked to 0, so the shift leaves 1 or -1 as it was. Zen 5 showed the masking in its recorded cases: FFFFFFFFH shifted by 32 stayed FFFFFFFFH, and a 64-bit 4000000000000001H shifted by C1H, read as 1, became 8000000000000002H. Where n may reach the width, BZHI of -1 gives the mask directly, as it keeps every bit for an index of 32 or more.

To set or test bit n of a variable, the compilers do not shift: they compile x | 1ULL << n to BTS, and x >> n & 1 to SHRX followed by an AND.

Width and speed#

The destination is written whole, so a 32-bit form clears bits 63:32. APX adds EVEX forms that reach its new registers. AMD’s Zen 5 instruction table lists SHLX, like SHL, as one macro-op with a latency of one cycle, three per cycle. SHLX belongs to BMI2, part of x86-64-v3.

Forms

Latency and throughput

Operation

What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.

n = count & (0x3F if OSIZE == 64 else 0x1F)   # the count is masked
dest.write(src << n)             # zeros come in from the bottom; no flag
                                 # changes, whatever the count

Operands

Flags

None: XED records no flag that the forms test or change.

Exceptions

The exception class is XED's name for the set of exception conditions that a form follows. How to read.

VEX forms

none in XED

EVEX forms

APX-EVEX-BMI

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

More BMI2 instructions

• BZHI
• MULX
• PDEP
• PEXT
• RORX
• SARX
• SHRX

More APX instructions

• PDEP
• PEXT
• POP2
• POP2P
• POPCNT
• POPP
• PUSH2
• PUSH2P
• PUSHP
• RCL
• RCR
• RDMSR
• ROL
• ROR
• RORX
• SAR
• SARX
• SBB
• SETcc
• SHL
• SHLD
• SHR
• SHRD
• SHRX
• STTILECFG
• SUB
• TILELOADD
• TILELOADDRS
• TILELOADDRST1
• TILELOADDT1
• TILESTORED
• TZCNT
• URDMSR
• UWRMSR
• WRMSRNS
• WRSSD
• WRSSQ
• WRUSSD
• WRUSSQ
• XOR

All 88 APX instructions