SHR

SHR shifts its operand right and fills the vacated high bits with zeros. For an unsigned number that is a division by 2^k rounded down, the same rounding as C’s, so GCC 14 and Clang 23 at -O2 compile both x / 8 and x >> 3 on an unsigned to shr eax, 3. Signed numbers need SAR, and a correction when the result must round toward zero.

In compiled code#

• Bit fields. A SHR and an AND take a field out of a word: both compilers turn (x >> 40) & 1 on a 64-bit x into shr rax, 40 and and eax, 1.
• The sign bit. (unsigned)x >> 31 is a single shr eax, 31, giving 1 for a negative int and 0 otherwise; the signed division by 2 on the SAR page starts with it.
• Word index. For a bit array of 64-bit words, n / 64 becomes shr rax, 6; the bit within the word, n % 64, comes free, since a shift by CL and a BT on a register both take their count modulo 64.
• Division by a constant. After the multiplication by a scaled reciprocal, a SHR of the product finishes an unsigned division (see DIV).

Count and flags#

The count is masked to 5 bits, or 6 for a 64-bit operand, as for SHL: both compilers compile x >> (n & 63) on a 64-bit x to shr rax, cl without the AND. The mask stays 5 bits for 8- and 16-bit operands, so a byte shifted by 8 to 31 becomes 0.

CF receives the last bit shifted out, so shr eax, 1 halves a value and leaves in CF whether it was odd. A shift by 1 sets OF to the old top bit; the note under the flags table lists where Intel’s manual and XED disagree. A count of 0 changes no flag at all, which Intel’s optimization manual names as the usual cause of partial flag stalls (Section 3.5.2.5).

SHRX from BMI2 takes its count from any register, writes a separate destination and leaves the flags alone; with -march=x86-64-v3, both compilers use it for x >> n. SHRD shifts in the bits of a second register instead of zeros, for values wider than a register. APX adds forms with a new destination and forms that leave the flags unchanged (NF).

In the optimization guide

What the optimization guide says about SHR, a line per claim. Each links to the claim in the guide, with its sources and where they differ.

Out of order

• Partial register and flag writes: A shift or rotate by CL leaves the flags alone when the count is zero, which is known only when it runs, so it depends on the old flags too.

Forms

Latency and throughput

Operation

What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.

a = dest.read()
n = count & (0x3F if OSIZE == 64 else 0x1F)   # the count is masked
r = a >> n                       # zeros come in from the top
if n != 0 and not nf:            # a count of 0 changes no flag; NF=1
                                 # (APX) none at all
    cf = a >> (n - 1) & 1        # the last bit shifted out: 0 once
                                 # n > OSIZE
    of = msb(a) if n == 1 else UNDEFINED   # the old sign bit
    sf = msb(r)                  # 0: a zero came in
    zf = r == 0
    pf = parity(r)
    af = UNDEFINED
dest.write(r)                    # even for a count of 0, a 32-bit register
                                 # gets bits 63:32 cleared

a = src.read()
n = count & (0x3F if OSIZE == 64 else 0x1F)   # the count is masked
r = a >> n                       # zeros come in from the top
if n != 0 and not nf:            # a count of 0 changes no flag; NF=1
                                 # none at all
    cf = a >> (n - 1) & 1        # the last bit shifted out: 0 once
                                 # n > OSIZE
    of = msb(a) if n == 1 else UNDEFINED   # the old sign bit
    sf = msb(r)                  # 0: a zero came in
    zf = r == 0
    pf = parity(r)
    af = UNDEFINED
dest.write(r)                    # the new destination: bits 63:OSIZE
                                 # cleared, even for 8 and 16 bits

Operands

Flags

Exceptions

The exception class is XED's name for the set of exception conditions that a form follows. How to read.

Legacy forms

none in XED

EVEX forms

APX-EVEX-INT

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

More General-purpose instructions

• NEG
• NOP
• NOT
• OR
• OUT
• OUTS
• PAUSE
• POP
• POPA
• POPF
• PUSH
• PUSHA
• PUSHF
• RCL
• RCR
• RET
• ROL
• ROR
• SALC
• SAR
• SBB
• SCAS
• SETcc
• SHL
• SHLD
• SHRD
• STC
• STD
• STI
• STOS
• SUB
• TEST
• UD0
• UD1
• UD2
• UDB
• XADD
• XCHG
• XLAT
• XOR

All 109 General-purpose instructions

More APX instructions

• PDEP
• PEXT
• POP2
• POP2P
• POPCNT
• POPP
• PUSH2
• PUSH2P
• PUSHP
• RCL
• RCR
• RDMSR
• ROL
• ROR
• RORX
• SAR
• SARX
• SBB
• SETcc
• SHL
• SHLD
• SHLX
• SHRD
• SHRX
• STTILECFG
• SUB
• TILELOADD
• TILELOADDRS
• TILELOADDRST1
• TILELOADDT1
• TILESTORED
• TZCNT
• URDMSR
• UWRMSR
• WRMSRNS
• WRSSD
• WRSSQ
• WRUSSD
• WRUSSQ
• XOR

All 88 APX instructions