x86-64.net

Instruction

SHR

Shifts an operand right, filling with zeros; APX adds three-operand forms and forms that leave the flags unchanged.

Extensions
Forms
48 (12 Legacy, 36 EVEX)
Data
Intel XED v2026.08.23

Forms

Every encoding of SHR that Intel XED knows, one row per XED instruction form (iform). How to read the notation.
InstructionEncodingRequires
SHR m8, imm8 SHR_MEMb_IMMbC0 /5 ibBase instruction set
SHR r8, imm8 SHR_GPR8_IMMbC0 /5 ibBase instruction set
SHR m16/32/64, imm8 SHR_MEMv_IMMbC1 /5 ibBase instruction set
SHR r16/32/64, imm8 SHR_GPRv_IMMbC1 /5 ibBase instruction set
SHR m8, imm8 SHR_MEMb_ONED0 /5Base instruction set
SHR r8, imm8 SHR_GPR8_ONED0 /5Base instruction set
SHR m16/32/64, imm8 SHR_MEMv_ONED1 /5Base instruction set
SHR r16/32/64, imm8 SHR_GPRv_ONED1 /5Base instruction set
SHR m8, CL SHR_MEMb_CLD2 /5Base instruction set
SHR r8, CL SHR_GPR8_CLD2 /5Base instruction set
SHR m16/32/64, CL SHR_MEMv_CLD3 /5Base instruction set
SHR r16/32/64, CL SHR_GPRv_CLD3 /5Base instruction set
SHR r8, imm8 SHR_GPR8i8_IMM8_APXEVEX.LLZ.NP.MAP4.WIG C0 /5 ibAPX_F
SHR m8, imm8 SHR_MEMi8_IMM8_APXEVEX.LLZ.NP.MAP4.WIG C0 /5 ibAPX_F
SHR r8, imm8 NF SHR_GPR8i8_IMM8_APX_N3EVEX.LLZ.NP.MAP4.WIG C0 /5 ib NF=1APX_F + APX_NCI_NDD_NF
SHR m8, imm8 NF SHR_MEMi8_IMM8_APX_N3EVEX.LLZ.NP.MAP4.WIG C0 /5 ib NF=1APX_F + APX_NCI_NDD_NF
SHR r16/32/64, r16/32/64, imm8 NDD NF optional SHR_GPRv_GPRv_IMM8_APX_N3EVEX.LLZ.NP.MAP4.SCALABLE C1 /5 ib ND=1 NF=0/1APX_F + APX_NCI_NDD_NF
SHR r16/32/64, m16/32/64, imm8 NDD NF optional SHR_GPRv_MEMv_IMM8_APX_N3EVEX.LLZ.NP.MAP4.SCALABLE C1 /5 ib ND=1 NF=0/1APX_F + APX_NCI_NDD_NF
SHR r8, imm8 SHR_GPR8i8_ONE_APXEVEX.LLZ.NP.MAP4.WIG D0 /5APX_F
SHR m8, imm8 SHR_MEMi8_ONE_APXEVEX.LLZ.NP.MAP4.WIG D0 /5APX_F
SHR r8, imm8 NF SHR_GPR8i8_ONE_APX_N3EVEX.LLZ.NP.MAP4.WIG D0 /5 NF=1APX_F + APX_NCI_NDD_NF
SHR m8, imm8 NF SHR_MEMi8_ONE_APX_N3EVEX.LLZ.NP.MAP4.WIG D0 /5 NF=1APX_F + APX_NCI_NDD_NF
SHR r8, r8, imm8 NDD NF optional SHR_GPR8i8_GPR8i8_ONE_APX_N3EVEX.LLZ.NP.MAP4.WIG D0 /5 ND=1 NF=0/1APX_F + APX_NCI_NDD_NF
SHR r8, m8, imm8 NDD NF optional SHR_GPR8i8_MEMi8_ONE_APX_N3EVEX.LLZ.NP.MAP4.WIG D0 /5 ND=1 NF=0/1APX_F + APX_NCI_NDD_NF
SHR r16/32/64, imm8 SHR_GPRv_ONE_APXEVEX.LLZ.NP.MAP4.SCALABLE D1 /5APX_F
SHR m16/32/64, imm8 SHR_MEMv_ONE_APXEVEX.LLZ.NP.MAP4.SCALABLE D1 /5APX_F
SHR r16/32/64, imm8 NF SHR_GPRv_ONE_APX_N3EVEX.LLZ.NP.MAP4.SCALABLE D1 /5 NF=1APX_F + APX_NCI_NDD_NF
SHR m16/32/64, imm8 NF SHR_MEMv_ONE_APX_N3EVEX.LLZ.NP.MAP4.SCALABLE D1 /5 NF=1APX_F + APX_NCI_NDD_NF
SHR r16/32/64, r16/32/64, imm8 NDD NF optional SHR_GPRv_GPRv_ONE_APX_N3EVEX.LLZ.NP.MAP4.SCALABLE D1 /5 ND=1 NF=0/1APX_F + APX_NCI_NDD_NF
SHR r16/32/64, m16/32/64, imm8 NDD NF optional SHR_GPRv_MEMv_ONE_APX_N3EVEX.LLZ.NP.MAP4.SCALABLE D1 /5 ND=1 NF=0/1APX_F + APX_NCI_NDD_NF
SHR r8, CL SHR_GPR8i8_CL_APXEVEX.LLZ.NP.MAP4.WIG D2 /5APX_F
SHR m8, CL SHR_MEMi8_CL_APXEVEX.LLZ.NP.MAP4.WIG D2 /5APX_F
SHR r8, CL NF SHR_GPR8i8_CL_APX_N3EVEX.LLZ.NP.MAP4.WIG D2 /5 NF=1APX_F + APX_NCI_NDD_NF
SHR m8, CL NF SHR_MEMi8_CL_APX_N3EVEX.LLZ.NP.MAP4.WIG D2 /5 NF=1APX_F + APX_NCI_NDD_NF
SHR r8, r8, CL NDD NF optional SHR_GPR8i8_GPR8i8_CL_APX_N3EVEX.LLZ.NP.MAP4.WIG D2 /5 ND=1 NF=0/1APX_F + APX_NCI_NDD_NF
SHR r8, m8, CL NDD NF optional SHR_GPR8i8_MEMi8_CL_APX_N3EVEX.LLZ.NP.MAP4.WIG D2 /5 ND=1 NF=0/1APX_F + APX_NCI_NDD_NF
SHR r16/32/64, CL SHR_GPRv_CL_APXEVEX.LLZ.NP.MAP4.SCALABLE D3 /5APX_F
SHR m16/32/64, CL SHR_MEMv_CL_APXEVEX.LLZ.NP.MAP4.SCALABLE D3 /5APX_F
SHR r16/32/64, CL NF SHR_GPRv_CL_APX_N3EVEX.LLZ.NP.MAP4.SCALABLE D3 /5 NF=1APX_F + APX_NCI_NDD_NF
SHR m16/32/64, CL NF SHR_MEMv_CL_APX_N3EVEX.LLZ.NP.MAP4.SCALABLE D3 /5 NF=1APX_F + APX_NCI_NDD_NF
SHR r16/32/64, r16/32/64, CL NDD NF optional SHR_GPRv_GPRv_CL_APX_N3EVEX.LLZ.NP.MAP4.SCALABLE D3 /5 ND=1 NF=0/1APX_F + APX_NCI_NDD_NF
SHR r16/32/64, m16/32/64, CL NDD NF optional SHR_GPRv_MEMv_CL_APX_N3EVEX.LLZ.NP.MAP4.SCALABLE D3 /5 ND=1 NF=0/1APX_F + APX_NCI_NDD_NF
SHR r8, r8, imm8 NDD NF optional SHR_GPR8i8_GPR8i8_IMM8_APX_N3EVEX.LLZ.NP.MAP4.WIG C0 /5 ib ND=1 NF=0/1APX_F + APX_NCI_NDD_NF
SHR r8, m8, imm8 NDD NF optional SHR_GPR8i8_MEMi8_IMM8_APX_N3EVEX.LLZ.NP.MAP4.WIG C0 /5 ib ND=1 NF=0/1APX_F + APX_NCI_NDD_NF
SHR r16/32/64, imm8 SHR_GPRv_IMM8_APXEVEX.LLZ.NP.MAP4.SCALABLE C1 /5 ibAPX_F
SHR m16/32/64, imm8 SHR_MEMv_IMM8_APXEVEX.LLZ.NP.MAP4.SCALABLE C1 /5 ibAPX_F
SHR r16/32/64, imm8 NF SHR_GPRv_IMM8_APX_N3EVEX.LLZ.NP.MAP4.SCALABLE C1 /5 ib NF=1APX_F + APX_NCI_NDD_NF
SHR m16/32/64, imm8 NF SHR_MEMv_IMM8_APX_N3EVEX.LLZ.NP.MAP4.SCALABLE C1 /5 ib NF=1APX_F + APX_NCI_NDD_NF

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

CPUID requirements and processors of the XED ISA sets above. Alternatives are separated by “or”; processors follow XED’s chip model, which covers AMD processors up to Zen 2.
ISA setCPUIDProcessors in XED
I186

No CPUID bit: part of the base instruction set.

Every x86-64 processor in XED’s model
I86

No CPUID bit: part of the base instruction set.

Every x86-64 processor in XED’s model
APX_F

APX_F
CPUID.(EAX=07H,ECX=1):EDX[21] APX_F

Nova Lake, Diamond Rapids
APX_F_N3

APX_F + APX_NCI_NDD_NF
CPUID.(EAX=07H,ECX=1):EDX[21] APX_F
CPUID.(EAX=29H,ECX=0):EBX[0] APX_NCI_NDD_NF

Nova Lake, Diamond Rapids

More General-purpose instructions

All 109 General-purpose instructions

More APX instructions

All 88 APX instructions

Sources

  1. Intel XED v2026.08.23 (commit 0bcb6237345c): forms, encodings, ISA sets, CPUID bits and chip model.
  2. Intel 64 and IA-32 Architectures Software Developer's Manual, Volume 2 (325383-092, June 2026)
  3. Intel 64 and IA-32 Architectures Software Developer's Manual, Volume 2 (325383-093, September 2026)
  4. Intel Advanced Performance Extensions (Intel APX) Architecture Specification, revision 7.0 (July 2025)

The tables are derived from Intel XED, Copyright Intel Corporation, licensed under the Apache License 2.0; x86-64.net converted and reformatted them. The text is our own.