SHRD

SHRD shifts its destination right and fills the vacated high bits from the bottom of a second register, as if the two formed one value of twice the width with the second register above. The second register is only read. It is the mirror image of SHLD, whose page says more about counts and speed.

Wide right shifts#

GCC 14 and Clang 23 at -O2 compile x >> 20 on an unsigned __int128 to shrd rax, rsi, 20 for the low half and a SHR by 20 for the high half; when only the low 64 bits are wanted, as in (uint64_t)(x >> 20), the SHRD alone remains. With n in a register, both shift the halves by CL and then fix up counts of 64 and more with two CMOVs, because the processor masks the count to 6 bits. For a signed __int128, the high half takes a SAR instead.

When source and destination are the same#

shrd eax, eax, n brings the low bits of EAX back in at the top, which is a rotate right, as ROR does it; Intel’s optimization manual notes that in Sandy Bridge this form with an immediate count has a latency of one cycle (Section 3.5.1.4). The flags differ from ROR’s, though: SHRD sets SF, ZF and PF from the result as well as CF and OF.

Edges#

• Count 0. The destination and the flags stay as they were (a 32-bit register still has bits 63:32 cleared).
• 16 bits. A 16-bit SHRD can be given a masked count of 17 to 31, for which both manuals leave the result undefined. Zen 5 shifted the 48 bits of two copies of the source above the destination, so that the source’s bits came in a second time, and cleared CF.
• Memory. The destination may be in memory; the second operand is always a register.

AMD’s Zen 5 guide gives SHRD, like SHLD, a latency of three cycles (Section 2.10.2). APX adds forms with a new destination and forms that leave the flags unchanged (NF).

In the optimization guide

What the optimization guide says about SHRD, a line per claim. Each links to the claim in the guide, with its sources and where they differ.

Golden Cove and Raptor Cove

• Integer execution: Port 1 alone runs the slower integer operations: multiplication, PDEP and PEXT, popcnt, bsr, crc32 and the double shifts with an immediate count, which LLVM’s models give a latency of three cycles and one per cycle.

Silvermont to Goldmont Plus

• Out-of-order and in-order execution: shld and shrd come from microcode at 64 bits, with a memory destination or a count in cl. sources differ

Skylake to Cooper Lake

• Integer execution: Port 1 alone runs integer multiplication, PDEP and PEXT, popcnt, lzcnt, tzcnt, bsf, bsr and the double shifts, with a latency of three cycles and one a cycle in LLVM’s models, as on Golden Cove.

Zen and Zen+

• Integer execution: SHLD is microcoded, taking four cycles in AMD’s spreadsheet, and LLVM treats double shifts as slow for -march=znver1. sources differ

Zen 2

• Integer execution: SHLD and SHRD are microcoded, and LLVM treats them as slow for -march=znver2, as it stops doing for Zen 3. sources differ

Zen 3

• Integer execution: SHLD and SHRD have a latency of three cycles, and LLVM’s -march=znver3 no longer treats them as slow, as it does for the Zen cores before. sources differ

Zen 4

• Integer execution: SHLD and SHRD have a latency of three cycles. sources differ

Forms

Latency and throughput

Operation

What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.

a = dest.read()
b = src.read()
n = count & (0x3F if OSIZE == 64 else 0x1F)   # the count is masked
if OSIZE == 16 and n > 16:
    # Intel's manual leaves the result and the flags undefined. Zen 5
    # shifts the 48 bits of src:src:dest, so that src comes in
    # again, and clears CF.
    dest.write(UNDEFINED)
    if not nf:
        of = sf = zf = UNDEFINED
        af = pf = cf = UNDEFINED
else:
    x = b << OSIZE | a           # src above dest
    r = low(x >> n)              # the bottom half: dest, with the low n
                                 # bits of src coming in from above
    if n != 0 and not nf:        # a count of 0 changes no flag; NF=1
                                 # (APX) none at all
        cf = a >> (n - 1) & 1    # the last bit shifted out
        flip = msb(r) ^ msb(a)
        of = flip if n == 1 else UNDEFINED   # the sign changed
        sf = msb(r)
        zf = r == 0
        pf = parity(r)
        af = UNDEFINED
    dest.write(r)                # even for a count of 0, a 32-bit
                                 # register gets bits 63:32 cleared

a = src1.read()
b = src2.read()
n = count & (0x3F if OSIZE == 64 else 0x1F)   # the count is masked
if OSIZE == 16 and n > 16:
    # Intel's manual leaves the result and the flags undefined
    dest.write(UNDEFINED)
    if not nf:
        of = sf = zf = UNDEFINED
        af = pf = cf = UNDEFINED
else:
    x = b << OSIZE | a           # src2 above src1
    r = low(x >> n)              # the bottom half: src1, with the low n
                                 # bits of src2 coming in from above
    if n != 0 and not nf:        # a count of 0 changes no flag; NF=1
                                 # none at all
        cf = a >> (n - 1) & 1    # the last bit shifted out
        flip = msb(r) ^ msb(a)
        of = flip if n == 1 else UNDEFINED   # the sign changed
        sf = msb(r)
        zf = r == 0
        pf = parity(r)
        af = UNDEFINED
    dest.write(r)                # the new destination: bits 63:OSIZE
                                 # cleared, even for 16 bits

Operands

Flags

Exceptions

The exception class is XED's name for the set of exception conditions that a form follows. How to read.

Legacy forms

none in XED

EVEX forms

APX-EVEX-INT

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

More General-purpose instructions

• NEG
• NOP
• NOT
• OR
• OUT
• OUTS
• PAUSE
• POP
• POPA
• POPF
• PUSH
• PUSHA
• PUSHF
• RCL
• RCR
• RET
• ROL
• ROR
• SALC
• SAR
• SBB
• SCAS
• SETcc
• SHL
• SHLD
• SHR
• STC
• STD
• STI
• STOS
• SUB
• TEST
• UD0
• UD1
• UD2
• UDB
• XADD
• XCHG
• XLAT
• XOR

All 109 General-purpose instructions

More APX instructions

• PDEP
• PEXT
• POP2
• POP2P
• POPCNT
• POPP
• PUSH2
• PUSH2P
• PUSHP
• RCL
• RCR
• RDMSR
• ROL
• ROR
• RORX
• SAR
• SARX
• SBB
• SETcc
• SHL
• SHLD
• SHLX
• SHR
• SHRX
• STTILECFG
• SUB
• TILELOADD
• TILELOADDRS
• TILELOADDRST1
• TILELOADDT1
• TILESTORED
• TZCNT
• URDMSR
• UWRMSR
• WRMSRNS
• WRSSD
• WRSSQ
• WRUSSD
• WRUSSQ
• XOR

All 88 APX instructions