SHRX

SHRX shifts its source right logically, zeros coming in at the top, by a count from any register, and writes a third register without touching the flags. It is SHR with the count anywhere but in CL and with a separate destination; SARX, whose page explains why such shifts leave the flags alone, is the arithmetic sibling and SHLX the left one. In Intel syntax the count comes last: shrx eax, edi, esi is EDI » ESI.

Unsigned shifts in C#

With -march=x86-64-v3, GCC 14 and Clang 23 at -O2 compile x >> n on an unsigned or uint64_t to a single SHRX, and a bit field read at a variable position, (x >> s) & ((1ULL << k) - 1), to SHRX followed by BZHI. A load can be the source: Clang folds *p >> n into shrx rax, qword ptr [rdi], rsi, while GCC loads with a MOV first. A shift by a constant stays shr rax, 7, as SHRX has no immediate form.

A count of the full width#

Only the low 5 bits of the count are used, 6 for a 64-bit operand. On Zen 5, a count of 32 left a 32-bit value unchanged and a count of 33 shifted it by 1; a count of 64 left a 64-bit value unchanged. C makes a shift by the width undefined for this reason, and code that needs x >> 32 to give 0 must ask for it: GCC and Clang compile n < 32 ? x >> n : 0 to SHRX, a CMP of the count with 32 and a CMOV that picks 0.

The masking can also help. Clang compiles x >> (32 - s) to neg sil and SHRX, since 32 - s and -s agree in their low 5 bits; GCC computes the subtraction.

Forms and speed#

The destination is written whole: a 32-bit form clears bits 63:32. APX adds EVEX forms that reach its new registers. AMD’s Zen 5 instruction table lists SHRX, like SHR, as one macro-op with a latency of one cycle, three per cycle. SHRX belongs to BMI2, part of x86-64-v3.

Forms

Latency and throughput

Operation

What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.

n = count & (0x3F if OSIZE == 64 else 0x1F)   # the count is masked
dest.write(src >> n)             # zeros come in from the top; no flag
                                 # changes, whatever the count

Operands

Flags

None: XED records no flag that the forms test or change.

Exceptions

The exception class is XED's name for the set of exception conditions that a form follows. How to read.

VEX forms

none in XED

EVEX forms

APX-EVEX-BMI

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

More BMI2 instructions

• BZHI
• MULX
• PDEP
• PEXT
• RORX
• SARX
• SHLX

More APX instructions

• PDEP
• PEXT
• POP2
• POP2P
• POPCNT
• POPP
• PUSH2
• PUSH2P
• PUSHP
• RCL
• RCR
• RDMSR
• ROL
• ROR
• RORX
• SAR
• SARX
• SBB
• SETcc
• SHL
• SHLD
• SHLX
• SHR
• SHRD
• STTILECFG
• SUB
• TILELOADD
• TILELOADDRS
• TILELOADDRST1
• TILELOADDT1
• TILESTORED
• TZCNT
• URDMSR
• UWRMSR
• WRMSRNS
• WRSSD
• WRSSQ
• WRUSSD
• WRUSSQ
• XOR

All 88 APX instructions