x86-64.net

Instruction

SHRX

Shifts the source right logically by a count in a register into a separate destination without touching the flags.

Extensions
Forms
8 (4 VEX, 4 EVEX)
Data
Intel XED v2026.08.23

Forms

Every encoding of SHRX that Intel XED knows, one row per XED instruction form (iform). How to read the notation.
InstructionEncodingRequires
SHRX r32, m32, r32 SHRX_GPR32d_MEMd_GPR32dVEX.LZ.F2.0F38.W0 F7 /rBMI2
SHRX r32, r32, r32 SHRX_GPR32d_GPR32d_GPR32dVEX.LZ.F2.0F38.W0 F7 /rBMI2
SHRX r64, m64, r64 64-bit mode only SHRX_GPR64q_MEMq_GPR64qVEX.LZ.F2.0F38.W1 F7 /rBMI2
SHRX r64, r64, r64 64-bit mode only SHRX_GPR64q_GPR64q_GPR64qVEX.LZ.F2.0F38.W1 F7 /rBMI2
SHRX r32, r32, r32 SHRX_GPR32i32_GPR32i32_GPR32i32_APXEVEX.LLZ.F2.0F38.W0 F7 /rAPX_F + BMI2
SHRX r32, m32, r32 SHRX_GPR32i32_MEMi32_GPR32i32_APXEVEX.LLZ.F2.0F38.W0 F7 /rAPX_F + BMI2
SHRX r64, r64, r64 SHRX_GPR64i64_GPR64i64_GPR64i64_APXEVEX.LLZ.F2.0F38.W1 F7 /rAPX_F + BMI2
SHRX r64, m64, r64 SHRX_GPR64i64_MEMi64_GPR64i64_APXEVEX.LLZ.F2.0F38.W1 F7 /rAPX_F + BMI2

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

CPUID requirements and processors of the XED ISA sets above. Alternatives are separated by “or”; processors follow XED’s chip model, which covers AMD processors up to Zen 2.
ISA setCPUIDProcessors in XED
BMI2

BMI2
CPUID.(EAX=07H,ECX=0):EBX[8] BMI2

Haswell, Broadwell, Skylake, Comet Lake, Cannon Lake, Ice Lake (client), Tiger Lake, Alder Lake, Arrow Lake, Panther Lake, Nova Lake, Skylake-SP, Cascade Lake, Cooper Lake, Ice Lake (server), Sapphire Rapids, Emerald Rapids, Granite Rapids, Diamond Rapids, Sierra Forest, Clearwater Forest, Knights Landing, Knights Mill, Zen, Zen+, Zen 2
APX_F_BMI2

APX_F + BMI2
CPUID.(EAX=07H,ECX=1):EDX[21] APX_F
CPUID.(EAX=07H,ECX=0):EBX[8] BMI2

Nova Lake, Diamond Rapids

More BMI2 instructions

More APX instructions

All 88 APX instructions

Sources

  1. Intel XED v2026.08.23 (commit 0bcb6237345c): forms, encodings, ISA sets, CPUID bits and chip model.
  2. Intel 64 and IA-32 Architectures Software Developer's Manual, Volume 2 (325383-092, June 2026)
  3. Intel Advanced Performance Extensions (Intel APX) Architecture Specification, revision 7.0 (July 2025)

The tables are derived from Intel XED, Copyright Intel Corporation, licensed under the Apache License 2.0; x86-64.net converted and reformatted them. The text is our own.