SHUFPD instruction (SSE2)

SHUFPD picks the low double of its result from the first operand and the high double from the second, one immediate bit choosing each: bit 0 takes element 0 or 1 of the first operand, bit 1 element 0 or 1 of the second. Bits 7:2 of the immediate are ignored. So 0 gives the same as UNPCKLPD, 3 the same as UNPCKHPD, and with one register as both operands, 1 swaps its two doubles. VSHUFPD repeats the choice in every 128-bit lane, with two more immediate bits per lane.

Zen 5’s recorded cases follow the two bits and nothing else: shufpd xmm12, xmmword ptr [mem], 0x2e (bits 1:0 are 10b) kept the destination’s low double and took the high double of memory, and shufpd xmm4, xmm4, 0x2f put element 1 in both halves. As a legacy SSE instruction it writes over its first operand, keeps bits 128 and up (see SSE and AVX), and needs its memory operand aligned to 16 bytes.

In compiled code

In our builds at -O2 for the default target, GCC 14 compiles _mm_shuffle_pd(a, b, 1) and the swap _mm_shuffle_pd(a, a, 1) to SHUFPD as written, and uses shufpd xmm0, xmm0, 1 itself in a loop over complex numbers, to swap the real and imaginary parts. Clang 23 emits SHUFPS with 4Eh instead, which moves the same 64-bit halves without the 66 prefix.

With -march=x86-64-v2, GCC writes the swap as PALIGNR of the register with itself by 8 bytes, an SSSE3 instruction, and keeps SHUFPD for two registers; Clang keeps SHUFPS. Where VEX is available, VPERMILPD does the one-register case without a copy.

Forms

Every encoding of SHUFPD that Intel XED knows, one row per XED instruction form (iform). How to read the notation.

Instruction	Encoding	Requires
`SHUFPD xmm, m128, imm8` SHUFPD_XMMpd_MEMpd_IMMb	`66 0F C6 /r ib`	SSE2
`SHUFPD xmm, xmm, imm8` SHUFPD_XMMpd_XMMpd_IMMb	`66 0F C6 /r ib`	SSE2

Data flow

Where the elements of the sources go, element 0 on the right; results that depend on a control value are drawn for an example. How to read.

Shuffle by immediate: the low double of the result comes from xmm1, the high one from xmm2, each picked by one bit of imm8.

Example: imm8 = 0x01 (0000 0001 in binary).

With imm8 = 0x01, result doubles 1 to 0: b0, a1.

Operation

What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.

src1 = xmm1.read()  # xmm1 as it was
for i in range(2):
    j = imm8 >> i & 1
    if i % 2 == 0:
        xmm1.q[i] = src1.q[j]
    else:
        xmm1.q[i] = src2.q[j]
# bits 128 and up of the register are unchanged

Run on AMD Zen 5 (EPYC 9645): 2 cases.

Operands

What each form reads and writes, as Intel XED records it: the operands of its syntax, in order, and the implicit ones that the syntax does not name. How to read.

Operand	Kind	Action
`SHUFPD xmm, xmm/m128, imm8`
`xmm`	explicit	read, write
`xmm/m128`	explicit	read
`imm8`	explicit	read

Flags

None: XED records no flag that the forms test or change.

Exceptions

The exception class is XED's name for the set of exception conditions that a form follows. How to read.

All forms: SSE_TYPE_4

Attributes

What else XED records about the forms. How to read.

Memory forms: aligned memory operand

Intrinsics

The C intrinsics of Clang 23.1.2 that compile to SHUFPD, each with the form it compiles to and the Clang options it needs. The forms come from compiling every intrinsic and decoding the result with Intel XED; all intrinsics A–Z explains the method.

Intrinsic	Compiles to
`_mm_shuffle_pd` `__m128d _mm_shuffle_pd(__m128d a, __m128d b, const int i)`	`SHUFPD xmm, xmm, imm8` Legacy -msse2

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

CPUID requirements and processors of the XED ISA sets above. Alternatives are separated by “or”; processors follow XED’s chip model, whose AMD processors end with Zen 2, and the CPU data of this site for Zen 3 to Zen 6.

ISA set	CPUID	Processors
`SSE2` SSE2	SSE2 `CPUID.01H:EDX[26]` SSE2	Every x86-64 processor in XED’s model and Zen 3 to Zen 6

More SSE2 instructions

All 124 SSE2 instructions

In compiled code#