SHUFPS instruction (SSE)

SHUFPS builds four singles from two vectors: the low two elements of the result come from the first operand and the high two from the second, each chosen by a 2-bit field of the immediate. Bits 1:0 and 3:2 pick elements 0 and 1 of the result from the first operand, bits 5:4 and 7:6 elements 2 and 3 from the second. With one register as both operands it permutes a single vector: shufps xmm0, xmm0, 0 copies element 0 into all four, and 1Bh reverses them. The _MM_SHUFFLE(d, c, b, a) macro of xmmintrin.h writes the four fields from the top down. SHUFPD does the same for doubles, with one bit per element, and VSHUFPS has a separate destination and repeats the choice in each 128-bit lane.

Zen 5’s recorded cases follow the fields: shufps xmm1, xmmword ptr [mem], 0x22 gave elements 2 and 0 of XMM1, then elements 2 and 0 of memory, and shufps xmm12, xmm6, 0xf9 elements 1 and 2 of XMM12, then element 3 of XMM6 twice. As a legacy SSE instruction it writes over its first operand, keeps bits 128 and up (see SSE and AVX) and needs a memory operand aligned to 16 bytes.

The shuffle compilers reach for

Before AVX2’s register form of VBROADCASTSS, this is how a single is broadcast: in our builds at -O2, for the default target and with -march=x86-64-v2, GCC 14 and Clang 23 compile _mm_set1_ps(x) to shufps xmm0, xmm0, 0. To split an array of (x, y) pairs into two arrays, both load two vectors and take the even elements with 88h and the odd ones with DDh. Since it reads two registers, it also stands in for blends: __builtin_shufflevector(a, b, 0, 5, 2, 7) is two SHUFPS with D8h for the default target, and one BLENDPS with SSE4.1. On integer data Clang prefers PSHUFD: a reversal written as SHUFPS on a cast __m128i comes out as pshufd xmm0, xmm0, 27, where GCC keeps SHUFPS.

Intel’s optimization manual builds its conversion of structures into arrays from SHUFPS, MOVLHPS and MOVHLPS, and notes that the Intel Core microarchitecture ran SHUFPS slower than the integer unpacks, a gap that the 128-bit shuffle unit of its Enhanced successor closed (Section 7.5.1.2). AMD’s spreadsheet for Zen 5 gives it a latency of 1 cycle on all four vector pipes.

Forms

Every encoding of SHUFPS that Intel XED knows, one row per XED instruction form (iform). How to read the notation.

Instruction	Encoding	Requires
`SHUFPS xmm, m128, imm8` SHUFPS_XMMps_MEMps_IMMb	`NP 0F C6 /r ib`	SSE
`SHUFPS xmm, xmm, imm8` SHUFPS_XMMps_XMMps_IMMb	`NP 0F C6 /r ib`	SSE

Data flow

Where the elements of the sources go, element 0 on the right; results that depend on a control value are drawn for an example. How to read.

Shuffle by immediate: the low two singles of the result come from xmm1, the high two from xmm2, each picked by two bits of imm8.

Example: imm8 = 0x4E (0100 1110 in binary).

With imm8 = 0x4E, result singles 3 to 0: b1, b0, a3, a2.

Operation

What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.

src1 = xmm1.read()  # xmm1 as it was
for i in range(4):
    j = imm8 >> 2 * i & 3
    if i % 4 < 2:
        xmm1.d[i] = src1.d[j]
    else:
        xmm1.d[i] = src2.d[j]
# bits 128 and up of the register are unchanged

Run on AMD Zen 5 (EPYC 9645): 2 cases.

Operands

What each form reads and writes, as Intel XED records it: the operands of its syntax, in order, and the implicit ones that the syntax does not name. How to read.

Operand	Kind	Action
`SHUFPS xmm, xmm/m128, imm8`
`xmm`	explicit	read, write
`xmm/m128`	explicit	read
`imm8`	explicit	read

Flags

None: XED records no flag that the forms test or change.

Exceptions

The exception class is XED's name for the set of exception conditions that a form follows. How to read.

All forms: SSE_TYPE_4

Attributes

What else XED records about the forms. How to read.

Memory forms: aligned memory operand

Intrinsics

The C intrinsics of Clang 23.1.2 that compile to SHUFPS, each with the form it compiles to and the Clang options it needs. The forms come from compiling every intrinsic and decoding the result with Intel XED; all intrinsics A–Z explains the method.

Intrinsic	Compiles to
`_mm_shuffle_ps` `__m128 _mm_shuffle_ps(__m128 a, __m128 b, const int mask)`	`SHUFPS xmm, xmm, imm8` Legacy -msse

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

CPUID requirements and processors of the XED ISA sets above. Alternatives are separated by “or”; processors follow XED’s chip model, whose AMD processors end with Zen 2, and the CPU data of this site for Zen 3 to Zen 6.

ISA set	CPUID	Processors
`SSE` SSE	SSE `CPUID.01H:EDX[25]` SSE	Every x86-64 processor in XED’s model and Zen 3 to Zen 6

More SSE instructions

All 65 SSE instructions

The shuffle compilers reach for#