SIDT instruction (System)

SIDT stores the interrupt descriptor table register, IDTR, to memory: first its 16-bit limit, then its base address, 8 bytes of it in 64-bit mode, so 10 bytes in all, or a 32-bit base and 6 bytes outside it. The layout is the operand of LIDT, so code at CPL 0 can save the register with SIDT and restore it later with LIDT. It is the twin of SGDT, whose page covers what the two share: operand-size prefixes changing nothing, a memory operand only, and the 286, which set the top byte of a 24-bit base to ones.

Readable at any privilege, unless UMIP

Neither manual makes SIDT privileged, and so a program could learn the address of the kernel’s IDT. UMIP, CR4 bit 11, makes it raise #GP(0) at CPL above 0, as for SGDT, SLDT, SMSW and STR; the SGDT page has the details.

The bytes around it

0F 01 /1 means SIDT only with a memory operand. With a register in the ModR/M byte the same opcode is MONITOR (0F 01 C8), MWAIT (C9), CLAC (CA) and STAC (CB), and with an F3 or F2 prefix, FRED’s ERETU and ERETS. GCC 14 and Clang 23 have no intrinsic for SIDT; C code stores into a packed structure of a 16-bit limit and the base with inline assembly.

The probe does not run SIDT, for the reasons its Operation section gives. AMD’s Zen 5 guide lists SIDT as microcoded.

Forms

Every encoding of SIDT that Intel XED knows, one row per XED instruction form (iform). How to read the notation.

Instruction	Encoding	Requires
`SIDT m16&32` not in 64-bit mode SIDT_MEMs	`0F 01 /1`	Base instruction set
`SIDT m16&64` 64-bit mode only SIDT_MEMs64	`0F 01 /1`	Base instruction set

Operation

What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.

if CPL > 0 and cr4 >> 11 & 1:    # CR4.UMIP
    fault(GP, 0)                 # Linux 7.2 emulates it: limit 0,
                                 # base FFFFFFFFFFFF0000H
dest.write(idtr)                 # the limit, 2 bytes, then the base:
                                 # 8 bytes in 64-bit mode, whatever
                                 # the operand size; 4 outside it
# a register operand: #UD

Not run on a processor: at CPL 3 with CR4.UMIP set, as Linux sets it, SIDT raises #GP(0), and Linux 7.2 emulates it for programs with made-up values; SIDT m16&32 does not exist in 64-bit mode, where the probe runs.

Operands

What each form reads and writes, as Intel XED records it: the operands of its syntax, in order, and the implicit ones that the syntax does not name. How to read.

Operand	Kind	Action
`SIDT m16&32` not in 64-bit mode `SIDT m16&64` 64-bit mode only
`m16&32, m16&64`	explicit	write
`IDTR`	implicit	read

Flags

None: XED records no flag that the forms test or change.

Attributes

What else XED records about the forms. How to read.

Forms not in 64-bit mode: may abort a TSX transaction

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

CPUID requirements and processors of the XED ISA sets above. Alternatives are separated by “or”; processors follow XED’s chip model, whose AMD processors end with Zen 2, and the CPU data of this site for Zen 3 to Zen 6.

ISA set	CPUID	Processors
`I286REAL` System	No CPUID bit: part of the base instruction set.	Every x86-64 processor in XED’s model and Zen 3 to Zen 6

SIDT

Readable at any privilege, unless UMIP

The bytes around it

Forms

Operation

Operands

Flags

Attributes

CPUID and processors

More System instructions

Sources

Readable at any privilege, unless UMIP#

The bytes around it#

Forms

Operation

Operands

Flags

Attributes

CPUID and processors

More System instructions

Sources

Readable at any privilege, unless UMIP

The bytes around it