Extensions
Forms
1 (1 Legacy)
Data
Intel XED v2026.08.23

Forms

Every encoding of SKINIT that Intel XED knows, one row per XED instruction form (iform). How to read the notation.
InstructionEncodingRequires
SKINIT EAX SKINIT_EAX0F 01 DESVM

Operation

What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.

if not efer >> 12 & 1:           # without SVM on, only where SVM-Lock
    r = cpuid_leaf(0x8000000A, 0)  # (EDX bit 2) or the device
    lock = r[3] >> 2 & 1         # exclusion vector of SKINIT
    r = cpuid_leaf(0x80000001, 0)  # (ECX bit 12) is there
    dev = r[2] >> 12 & 1
    if not lock and not dev:
        fault(UD)
if CPL > 0:
    fault(GP, 0)
if intercepted(0x86):
    vm_exit(0x86)                # in a guest: to its hypervisor
a = slb.read() & 0xFFFF0000      # the secure loader block, 64 KB
init_state()                     # as an INIT signal leaves it, CR0
                                 # with PE set: protected mode, no
                                 # paging
set_rflags(0)                    # bit 1 alone
cs = 0x08                        # flat 32-bit code
ss = 0x10                        # flat 32-bit stack
efer = 0
eax = a
edx = cpuid_leaf(1, 0)[0]        # family, model and stepping
esp = a + 0x10000                # the SL's stack, above the SLB
ebx = ecx = ebp = esi = edi = 0
r8 = r9 = r10 = r11 = 0
r12 = r13 = r14 = r15 = 0
msr[VM_CR] = msr[VM_CR] | 7      # DPD, R_INIT and DIS_A20M set
gif = 0
set_cpl(0)
n = phys_read(a + 2, 16)         # the SL's length; the SLB's 64 KB
                                 # kept from devices, and its first
                                 # n bytes hashed into the TPM
rip = a + phys_read(a, 16)       # the SL's entry point

Run on AMD Zen 5 (EPYC 9645): 2 cases. Every one raised an exception, at CPL 3, where the probe runs.

Operands

What each form reads and writes, as Intel XED records it: the operands of its syntax, in order, and the implicit ones that the syntax does not name. How to read.
OperandKindAction
SKINIT EAX
EAXexplicitread

Flags

None: XED records no flag that the forms test or change.

Attributes

What else XED records about the forms. How to read.

All forms
not in real-address mode

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

CPUID requirements and processors of the XED ISA sets above. Alternatives are separated by “or”; processors follow XED’s chip model, whose AMD processors end with Zen 2, and the CPU data of this site for Zen 3 to Zen 6.
ISA setCPUIDProcessors
SVM

SVM
CPUID.80000001H:ECX[2] SVM

K10 (Family 10h), Bulldozer, Piledriver, Zen, Zen+, Zen 2, Zen 3, Zen 4, Zen 5, Zen 6

More SVM instructions

Sources

  1. Intel XED v2026.08.23 (commit 0bcb6237345c): forms, encodings, operands, flags, exception classes, attributes, ISA sets, CPUID bits and chip model.
  2. The CPU data of x86-64.net: Zen 3 to Zen 6, from GCC’s -march feature sets and AMD’s Processor Programming References, which the page of each processor cites.
  3. AMD64 Architecture Programmer's Manual, Volume 3: General-Purpose and System Instructions (24594, rev. 3.36, March 2024), Wayback Machine copy of AMD's PDF
  4. AMD64 Architecture Programmer's Manual, Volume 2: System Programming (24593, rev. 3.42, March 2024), Wayback Machine copy of AMD's PDF

The tables are derived from Intel XED, Copyright Intel Corporation, licensed under the Apache License 2.0; x86-64.net converted and reformatted them. The text is our own.