Instruction
SKINIT
Reinitializes the processor securely and starts the secure loader at the physical address in EAX after measuring it; AMD SVM.
AMD's virtualization extension: Intel processors implement VMX instead.
- Extensions
- Forms
- 1 (1 Legacy)
- Data
- Intel XED v2026.08.23
Forms
| Instruction | Encoding | Requires |
|---|---|---|
SKINIT EAX
SKINIT_EAX | 0F 01 DE | SVM |
Operation
What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.
if not efer >> 12 & 1: # without SVM on, only where SVM-Lock
r = cpuid_leaf(0x8000000A, 0) # (EDX bit 2) or the device
lock = r[3] >> 2 & 1 # exclusion vector of SKINIT
r = cpuid_leaf(0x80000001, 0) # (ECX bit 12) is there
dev = r[2] >> 12 & 1
if not lock and not dev:
fault(UD)
if CPL > 0:
fault(GP, 0)
if intercepted(0x86):
vm_exit(0x86) # in a guest: to its hypervisor
a = slb.read() & 0xFFFF0000 # the secure loader block, 64 KB
init_state() # as an INIT signal leaves it, CR0
# with PE set: protected mode, no
# paging
set_rflags(0) # bit 1 alone
cs = 0x08 # flat 32-bit code
ss = 0x10 # flat 32-bit stack
efer = 0
eax = a
edx = cpuid_leaf(1, 0)[0] # family, model and stepping
esp = a + 0x10000 # the SL's stack, above the SLB
ebx = ecx = ebp = esi = edi = 0
r8 = r9 = r10 = r11 = 0
r12 = r13 = r14 = r15 = 0
msr[VM_CR] = msr[VM_CR] | 7 # DPD, R_INIT and DIS_A20M set
gif = 0
set_cpl(0)
n = phys_read(a + 2, 16) # the SL's length; the SLB's 64 KB
# kept from devices, and its first
# n bytes hashed into the TPM
rip = a + phys_read(a, 16) # the SL's entry point
Run on AMD Zen 5 (EPYC 9645): 2 cases. Every one raised an exception, at CPL 3, where the probe runs.
Operands
| Operand | Kind | Action |
|---|---|---|
SKINIT EAX | ||
EAX | explicit | read |
Flags
None: XED records no flag that the forms test or change.
Attributes
What else XED records about the forms. How to read.
- All forms
- not in real-address mode
CPUID and processors
Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.
More SVM instructions
Sources
- Intel XED v2026.08.23 (commit
0bcb6237345c): forms, encodings, operands, flags, exception classes, attributes, ISA sets, CPUID bits and chip model. - The CPU data of x86-64.net: Zen 3 to Zen 6, from GCC’s
-marchfeature sets and AMD’s Processor Programming References, which the page of each processor cites. - AMD64 Architecture Programmer's Manual, Volume 3: General-Purpose and System Instructions (24594, rev. 3.36, March 2024), Wayback Machine copy of AMD's PDF
- AMD64 Architecture Programmer's Manual, Volume 2: System Programming (24593, rev. 3.42, March 2024), Wayback Machine copy of AMD's PDF
The tables are derived from Intel XED, Copyright Intel Corporation, licensed under the Apache License 2.0; x86-64.net converted and reformatted them. The text is our own.