SLWPCB instruction (LWP)

Forms

Every encoding of SLWPCB that Intel XED knows, one row per XED instruction form (iform). How to read the notation.

Instruction	Encoding	Requires
`SLWPCB r32/64` SLWPCB_GPRyy	`XOP.LZ.NP.09.WIG 12 /1`	LWP

Latency and throughput

What the scheduling models of LLVM 23.1.2 give for each form, not measurements: latency / reciprocal throughput in cycles, the ports under them. A row is a model, or models that agree; a dash, a form that its processors lack. Memory forms: latency from the address, ports without the load and store units. Which processors each model covers.

Model	`r32/64`
Piledriver	100 / 0.5EX0 EX1

Operation

What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.

features = cpuid_leaf(0x80000001, 0)[2]
if not features >> 15 & 1:
    fault(UD)                    # CPUID: no LWP
if not xcr0 >> 62 & 1:           # LWP's state not enabled by the
    fault(UD)                    # OS
a = lwp_cbaddr
if a:                            # running: the counters and the
    e = cpuid_leaf(0x8000001C, 0)  # head that LWP keeps go to
    off = e[1] >> 24             # the LWPCB
    n = e[1] >> 16 & 0xFF        # LwpMaxEvents
    opts = load(a, 32)
    for i in range(1, n + 1):
        if opts >> i & 1:
            at = a + off + 8 * i - 4
            c = lwp_count[i] & 0x3FFFFFF
            store(at, 32, c)     # EventCounter i
    store(a + 16, 32, lwp_head)
dest.write(a)                    # its address, or 0: LWP is off
# a record that LWP has gathered but not stored is stored first.
# The address is DS's offset, its base 0 in 64-bit mode

Run on AMD Zen 5 (EPYC 9645): 2 cases. Its cases ran where CPUID reported no LWP, and every one raised an exception.

Operands

What each form reads and writes, as Intel XED records it: the operands of its syntax, in order, and the implicit ones that the syntax does not name. How to read.

Operand	Kind	Action
`SLWPCB r32/64`
`r32/64`	explicit	write

Flags

None: XED records no flag that the forms test or change.

Intrinsics

The C intrinsics of Clang 23.1.2 that compile to SLWPCB, each with the form it compiles to and the Clang options it needs. The forms come from compiling every intrinsic and decoding the result with Intel XED; all intrinsics A–Z explains the method.

Intrinsic	Compiles to
`__slwpcb` `void * __slwpcb(void)`	`SLWPCB r32/64` XOP.LZ -mlwp

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

CPUID requirements and processors of the XED ISA sets above. Alternatives are separated by “or”; processors follow XED’s chip model, whose AMD processors end with Zen 2, and the CPU data of this site for Zen 3 to Zen 6.

ISA set	CPUID	Processors
`LWP` LWP	LWP `CPUID.80000001H:ECX[15]` LWP	Bulldozer, Piledriver

SLWPCB