x86-64.net

Instruction

SMSW

Stores the machine status word, the low bits of CR0, to a register or memory; CR4.UMIP keeps it from user code.

Extensions
Forms
2 (2 Legacy)
Data
Intel XED v2026.08.23

Forms

Every encoding of SMSW that Intel XED knows, one row per XED instruction form (iform). How to read the notation.
InstructionEncodingRequires
SMSW m16 SMSW_MEMw0F 01 /4Base instruction set
SMSW r16/32/64 SMSW_GPRv0F 01 /4Base instruction set

Operation

What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.

if CPL > 0 and cr4 >> 11 & 1:    # CR4.UMIP
    fault(GP, 0)                 # Linux 7.2 emulates it: 80050033H,
                                 # leaving bits 63:32 of a 32-bit
                                 # register as they were
dest.write(cr0)                  # memory and 16-bit registers: bits
                                 # 15:0 of CR0, the machine status
                                 # word; 32: bits 31:0; 64: all of it
# Intel's table of forms leaves bits 31:16 of a 32-bit register
# undefined; its text on 64-bit mode and AMD's manual store CR0's

Not run on a processor: at CPL 3 with CR4.UMIP set, as Linux sets it, SMSW raises #GP(0), and Linux 7.2 emulates it for programs with made-up values.

Operands

What each form reads and writes, as Intel XED records it: the operands of its syntax, in order, and the implicit ones that the syntax does not name. How to read.
OperandKindAction
SMSW m16
m16explicitwrite
CR0implicitread
SMSW r16/32/64
r16/32/64explicitwrite
CR0implicitread

Flags

None: XED records no flag that the forms test or change.

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

CPUID requirements and processors of the XED ISA sets above. Alternatives are separated by “or”; processors follow XED’s chip model, whose AMD processors end with Zen 2, and the CPU data of this site for Zen 3 to Zen 6.
ISA setCPUIDProcessors
I286REAL

No CPUID bit: part of the base instruction set.

Every x86-64 processor in XED’s model and Zen 3 to Zen 6

More System instructions

Sources

  1. Intel XED v2026.08.23 (commit 0bcb6237345c): forms, encodings, operands, flags, exception classes, attributes, ISA sets, CPUID bits and chip model.
  2. The CPU data of x86-64.net: Zen 3 to Zen 6, from GCC’s -march feature sets and AMD’s Processor Programming References, which the page of each processor cites.
  3. Intel 64 and IA-32 Architectures Software Developer's Manual, Volume 2 (325383-093, September 2026): Volume 2B, page 4-659 (SMSW)
  4. Intel 64 and IA-32 Architectures Software Developer's Manual, Volume 3 (325384-093, September 2026)

The tables are derived from Intel XED, Copyright Intel Corporation, licensed under the Apache License 2.0; x86-64.net converted and reformatted them. The text is our own.