SQRTPD instruction (SSE2)

SQRTPD takes the correctly rounded square roots of two doubles, each as IEEE 754 requires; SQRTSD takes that of the low one and describes the test that guards errno, and SQRTPS the special inputs for the single-precision form, which hold here as well: -0’s root is -0, and any other negative number’s, -infinity included, is invalid, giving the quiet indefinite with IE set. On Zen 5, with DAZ set and masked, sqrtpd xmm8, xmmword ptr [mem] took the roots of +infinity and -infinity from memory and gave +infinity and FFF8000000000000h, the indefinite, with IE set. In a case with DAZ clear, the root of the smallest denormal double, 5e-324, came out correctly rounded to a true subnormal result, about 2.22e-162, rather than to zero or to an estimate: this instruction gives an exact answer for a denormal operand, unlike RCPPS and RSQRTPS, whose recorded cases turn one into infinity. With IM clear, so IE unmasked, a signaling NaN or a negative operand instead makes SQRTPD fault with #XM: two such cases were recorded, one with every exception unmasked, and both left the destination register exactly as it was.

In compiled code

C’s sqrt may set errno for a negative argument, which no instruction can, so GCC 14 and Clang 23 at -O2 compile a bare sqrt(x) to a UCOMISD test and a call to the library for a negative x, as SQRTSD’s page describes; a sum of squares, which is never negative, skips the test in both. With -fno-math-errno the test goes away: GCC keeps a loop of sqrt calls scalar, one SQRTSD per element, while Clang moves it to SQRTPD, two doubles at a time.

AMD’s latency spreadsheet for Zen 5 gives SQRTPD the same figures as SQRTSD: 20 cycles and 0.133 per cycle, on pipe FP1, against 14 cycles for single precision, and the merge optimization of its guide (Section 2.11.5) applies equally. The memory form needs 16 bytes aligned to 16, and VSQRTPD is the VEX and EVEX form.

In the optimization guide

What the optimization guide says about SQRTPD, a line per claim. Each links to the claim in the guide, with its sources and where they differ.

Bulldozer to Excavator

Vectors and floating point: Division and square root run in each FMA unit’s own divider: DIVPD takes 27 cycles and SQRTPD 38 on Bulldozer and Piledriver, while AMD’s table for Steamroller gives single precision fewer cycles, 18 for DIVPS, and double precision more, 33 and 44. sources differ

Jaguar and Puma

Vectors and floating point: Division and square root iterate in the multiply unit of pipe 1, not pipelined and without early exit: DIVSS takes 14 cycles, DIVPS, DIVPD and DIVSD 19, SQRTSS 16, SQRTPS 21 and SQRTPD 27, and a 256-bit form twice as long. sources differ

Skylake to Cooper Lake

Vectors on all parts: Division and square root are pipelined, and 256-bit forms have the latency of 128-bit ones: LLVM’s models give DIVPS 11 cycles, SQRTPS 12, DIVPD 14 and SQRTPD 18.

Forms

Every encoding of SQRTPD that Intel XED knows, one row per XED instruction form (iform). How to read the notation.

Instruction	Encoding	Requires
`SQRTPD xmm, m128` SQRTPD_XMMpd_MEMpd	`66 0F 51 /r`	SSE2
`SQRTPD xmm, xmm` SQRTPD_XMMpd_XMMpd	`66 0F 51 /r`	SSE2

Data flow

Where the elements of the sources go, element 0 on the right; results that depend on a control value are drawn for an example. How to read.

Element-wise: each double of the result comes from the double in the same place in each source.

Result double i comes from double i of xmm2. Result doubles 1 to 0: r1, r0.

Operation

What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.

for i in range(2):
    xmm1.f64[i] = sqrt(src2.f64[i])
# bits 128 and up of the register are unchanged

Run on AMD Zen 5 (EPYC 9645): 9 cases.

Operands

What each form reads and writes, as Intel XED records it: the operands of its syntax, in order, and the implicit ones that the syntax does not name. How to read.

Operand	Kind	Action
`SQRTPD xmm, xmm/m128`
`xmm`	explicit	write
`xmm/m128`	explicit	read

Flags

None: XED records no flag that the forms test or change.

Exceptions

The exception class is XED's name for the set of exception conditions that a form follows. How to read.

All forms: SSE_TYPE_2

Attributes

What else XED records about the forms. How to read.

All forms: follows MXCSR
Memory forms: aligned memory operand

Intrinsics

The C intrinsics of Clang 23.1.2 that compile to SQRTPD, each with the form it compiles to and the Clang options it needs. The forms come from compiling every intrinsic and decoding the result with Intel XED; all intrinsics A–Z explains the method.

Intrinsic	Compiles to
`_mm_sqrt_pd` `__m128d _mm_sqrt_pd(__m128d __a)`	`SQRTPD xmm, xmm` Legacy -msse2

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

CPUID requirements and processors of the XED ISA sets above. Alternatives are separated by “or”; processors follow XED’s chip model, whose AMD processors end with Zen 2, and the CPU data of this site for Zen 3 to Zen 6.

ISA set	CPUID	Processors
`SSE2` SSE2	SSE2 `CPUID.01H:EDX[26]` SSE2	Every x86-64 processor in XED’s model and Zen 3 to Zen 6

More SSE2 instructions

All 124 SSE2 instructions

In compiled code#