SQRTPS instruction (SSE)

SQRTPS takes the square roots of four singles, each correctly rounded as IEEE 754 requires; SQRTSS takes that of the lowest one, and VSQRTPS is the VEX and EVEX form. The root of -0 is -0. The root of any other negative number, -infinity included, is an invalid operation: it sets IE and, with the exception masked, gives the QNaN floating-point indefinite, FFC00000H.

C’s sqrtf and errno

C’s sqrtf may set errno for a negative argument, as glibc’s does, which no instruction can. GCC 14 and Clang 23 at -O2 therefore compile sqrtf(x) to SQRTSS behind a compare that sends negative arguments to the library function, and neither vectorizes a loop that calls it. With -fno-math-errno the compare goes away, and the loop a[i] = sqrtf(b[i]) over floats becomes SQRTPS.

With -ffast-math both go further and drop SQRTPS from that loop: they multiply x by RSQRTPS’s estimate of 1/sqrt(x), refined by one Newton-Raphson step, with a fix-up so that a zero still gives zero. The result is close, not correctly rounded. GCC does the same for a scalar 1.0f / sqrtf(x), with RSQRTSS.

Speed

Intel’s optimization guide gives SQRTPS the same figures as DIVPS: about 14 cycles before Skylake, not pipelined, the 256-bit VSQRTPS of Sandy Bridge twice that, and pipelined on Skylake. Its comparison of the alternatives (Section 15.12) recommends SQRTPS where all 24 bits matter, and sequences built on RSQRTPS where about 22 or 11 bits are enough, though on Skylake the 22-bit one is not always the faster. AMD’s guide for Zen 5 runs every square root and division in the same unit (Section 2.11.1), and names square root among the operations that run again at a longer latency on a denormal input or result unless DAZ and FTZ are set (Section 2.11.2; see MULPS).

In the optimization guide

What the optimization guide says about SQRTPS, a line per claim. Each links to the claim in the guide, with its sources and where they differ.

Skylake to Cooper Lake

Vectors on all parts: Division and square root are pipelined, and 256-bit forms have the latency of 128-bit ones: LLVM’s models give DIVPS 11 cycles, SQRTPS 12, DIVPD 14 and SQRTPD 18.

Forms

Every encoding of SQRTPS that Intel XED knows, one row per XED instruction form (iform). How to read the notation.

Instruction	Encoding	Requires
`SQRTPS xmm, m128` SQRTPS_XMMps_MEMps	`NP 0F 51 /r`	SSE
`SQRTPS xmm, xmm` SQRTPS_XMMps_XMMps	`NP 0F 51 /r`	SSE

Data flow

Where the elements of the sources go, element 0 on the right; results that depend on a control value are drawn for an example. How to read.

Element-wise: each single of the result comes from the single in the same place in each source.

Result single i comes from single i of xmm2. Result singles 3 to 0: r3, r2, r1, r0.

Operation

What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.

for i in range(4):
    xmm1.f32[i] = sqrt(src2.f32[i])
# bits 128 and up of the register are unchanged

Run on AMD Zen 5 (EPYC 9645): 2 cases.

Operands

What each form reads and writes, as Intel XED records it: the operands of its syntax, in order, and the implicit ones that the syntax does not name. How to read.

Operand	Kind	Action
`SQRTPS xmm, xmm/m128`
`xmm`	explicit	write
`xmm/m128`	explicit	read

Flags

None: XED records no flag that the forms test or change.

Exceptions

The exception class is XED's name for the set of exception conditions that a form follows. How to read.

All forms: SSE_TYPE_2

Attributes

What else XED records about the forms. How to read.

All forms: follows MXCSR
Memory forms: aligned memory operand

Intrinsics

The C intrinsics of Clang 23.1.2 that compile to SQRTPS, each with the form it compiles to and the Clang options it needs. The forms come from compiling every intrinsic and decoding the result with Intel XED; all intrinsics A–Z explains the method.

Intrinsic	Compiles to
`_mm_sqrt_ps` `__m128 _mm_sqrt_ps(__m128 __a)`	`SQRTPS xmm, xmm` Legacy -msse

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

CPUID requirements and processors of the XED ISA sets above. Alternatives are separated by “or”; processors follow XED’s chip model, whose AMD processors end with Zen 2, and the CPU data of this site for Zen 3 to Zen 6.

ISA set	CPUID	Processors
`SSE` SSE	SSE `CPUID.01H:EDX[25]` SSE	Every x86-64 processor in XED’s model and Zen 3 to Zen 6

More SSE instructions

All 65 SSE instructions

C’s sqrtf and errno#

Speed#