SQRTSD instruction (SSE2)

SQRTSD takes the correctly rounded square root of the low double of its source and keeps the high double of the destination. It is SSE2, so every x86-64 processor has it, and it is what C’s sqrt compiles to. SQRTSS describes the scalar roots in more detail, from the test that guards errno to the merge with the old destination, and SQRTPS the special inputs; this page adds what Zen 5 recorded for doubles and where the compilers drop the test. In the recorded cases:

the root of the largest double, 1.7976931348623157e308, was 5FEFFFFFFFFFFFFFh, about 1.3407807929942596e154, with PE set, since it is not exact;
the smallest denormal, read from memory with DAZ set, counted as zero: the root was +0 and no flag was set;
the high double of the destination stayed as it was in both.

When the test goes away

In our builds at -O2, GCC 14 and Clang 23 compile sqrt(x) to a UCOMISD against zero, a jump to the library’s sqrt for a negative x, and SQRTSD otherwise. For a distance, sqrt(dx*dx + dy*dy), both emit SQRTSD alone, with no test and no option, since a sum of squares is never negative. A loop of sqrt calls stays scalar at -O2 in both, each element with its own test and call; with -fno-math-errno, GCC keeps it scalar with one SQRTSD per element and Clang moves to SQRTPD.

_mm_sqrt_sd(a, b) returns the root of the low double of b with the high double of a, the instruction’s own operand order: Clang emits sqrtsd xmm0, xmm1, while GCC first copies the low double with MOVSD and then takes the root in place.

AMD’s latency spreadsheet for Zen 5 lists SQRTSD at 20 cycles and 0.133 per cycle on pipe FP1, against 14 cycles for single precision, and the merge optimization of its guide covers it (Section 2.11.5). The memory form reads eight bytes at any alignment; the legacy form keeps bits 255:128 (see mixing SSE and AVX), and VSQRTSD is the VEX and EVEX form.

In the optimization guide

What the optimization guide says about SQRTSD, a line per claim. Each links to the claim in the guide, with its sources and where they differ.

Out of order

Partial register and flag writes: Zen 3 to Zen 5 let sqrtss, cvtsi2sd and other scalar instructions skip the wait for an XMM register whose upper part is known to be zero, so AMD advises zeroing a vector register when done with it.
Partial register and flag writes: LLVM breaks the false dependency itself, with an xorps before cvtsi2sd, sqrtss and the other partial writers whose register was written within the last 64 instructions.

Zen and Zen+

Vectors and floating point: Division and square root run on pipe 3: AMD’s spreadsheet gives divps 10 cycles, DIVSD 13, sqrtss 14 and SQRTSD 20, as LLVM’s model does, and LLVM tunes -march=znver1 to compute square roots with these instructions rather than an estimate.

Forms

Every encoding of SQRTSD that Intel XED knows, one row per XED instruction form (iform). How to read the notation.

Instruction	Encoding	Requires
`SQRTSD xmm, m64` SQRTSD_XMMsd_MEMsd	`F2 0F 51 /r`	SSE2
`SQRTSD xmm, xmm` SQRTSD_XMMsd_XMMsd	`F2 0F 51 /r`	SSE2

Data flow

Where the elements of the sources go, element 0 on the right; results that depend on a control value are drawn for an example. How to read.

Scalar: only the low double is computed; the other double comes from xmm1.

Result double 0 is computed from double 0 of xmm2; double 1 is that of xmm1. Result doubles 1 to 0: a1, r0.

Operation

What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.

xmm1.f64[0] = sqrt(src2.f64[0])
# xmm1.q[1] keeps its value
# bits 128 and up of the register are unchanged

Run on AMD Zen 5 (EPYC 9645): 2 cases.

Operands

What each form reads and writes, as Intel XED records it: the operands of its syntax, in order, and the implicit ones that the syntax does not name. How to read.

Operand	Kind	Action
`SQRTSD xmm, xmm/m64`
`xmm`	explicit	read, write
`xmm/m64`	explicit	read

Flags

None: XED records no flag that the forms test or change.

Exceptions

The exception class is XED's name for the set of exception conditions that a form follows. How to read.

All forms: SSE_TYPE_3

Attributes

What else XED records about the forms. How to read.

All forms: follows MXCSR

Intrinsics

The C intrinsics of Clang 23.1.2 that compile to SQRTSD, each with the form it compiles to and the Clang options it needs. The forms come from compiling every intrinsic and decoding the result with Intel XED; all intrinsics A–Z explains the method.

Intrinsic	Compiles to
`_mm_sqrt_sd` `__m128d _mm_sqrt_sd(__m128d __a, __m128d __b)`	`SQRTSD xmm, xmm` Legacy -msse2

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

CPUID requirements and processors of the XED ISA sets above. Alternatives are separated by “or”; processors follow XED’s chip model, whose AMD processors end with Zen 2, and the CPU data of this site for Zen 3 to Zen 6.

ISA set	CPUID	Processors
`SSE2` SSE2	SSE2 `CPUID.01H:EDX[26]` SSE2	Every x86-64 processor in XED’s model and Zen 3 to Zen 6

More SSE2 instructions

All 124 SSE2 instructions

When the test goes away#