SQRTSS instruction (SSE)

SQRTSS takes the square root of the low single of its source, correctly rounded under MXCSR’s rounding mode, and leaves singles 1 to 3 of the destination as they were. SQRTPS, the packed form, covers the special inputs and why C’s sqrtf needs a test before the instruction; VSQRTSS is the VEX and EVEX form. On Zen 5, the recorded root of -0.5 was the indefinite FFC00000h with IE set, and the 1.5, 2.5 and -2.5 above it stayed; the root of -infinity, read from memory with every exception masked, gave the same.

sqrtf in compiled code

In our builds at -O2 for the x86-64 baseline, GCC 14 and Clang 23 compile sqrtf(x) to a UCOMISS of x against zero that sends a negative argument to the library function, which can set errno, and to this instruction otherwise. When the compiler can see that the argument is not negative, as in sqrtf(fabsf(x)), the test goes away even without -fno-math-errno: an ANDPS clears the sign and the root follows.

For sqrtf(*p) neither compiler uses the memory form. Both load the single with MOVSS, which zeroes bits 127:32, and take the root in place, since sqrtss xmm0, [rdi] would merge its result into whatever XMM0 held before.

The merge

Because three singles come from the old destination, the instruction waits for whatever last wrote that register, even in scalar code that never reads them. AMD’s guide for Zen 5 names it among the instructions that skip that wait when the upper bits are known to be zero (Section 2.11.5). The compilers part ways on x + sqrtf(x) with -fno-math-errno: GCC copies x with MOVAPS and computes sqrtss xmm0, xmm0, whose only input is the argument itself, while Clang writes sqrtss xmm1, xmm0 into a register the function never wrote.

AMD’s latency spreadsheet for Zen 5 gives it 14 cycles, at 0.222 per cycle, on pipe FP1, as for SQRTPS. The memory form reads four bytes at any alignment, and the legacy form keeps bits 255:128 of its register (see mixing SSE and AVX). SQRTSD is the double-precision form.

In the optimization guide

What the optimization guide says about SQRTSS, a line per claim. Each links to the claim in the guide, with its sources and where they differ.

Out of order

Partial register and flag writes: Zen 3 to Zen 5 let sqrtss, cvtsi2sd and other scalar instructions skip the wait for an XMM register whose upper part is known to be zero, so AMD advises zeroing a vector register when done with it.
Partial register and flag writes: LLVM breaks the false dependency itself, with an xorps before cvtsi2sd, sqrtss and the other partial writers whose register was written within the last 64 instructions.

Bulldozer to Excavator

Vectors and floating point: Scalar instructions such as SQRTSS and CVTSI2SD keep the rest of their destination and wait for its last write, unless the core knows that part to be zero, which it tracks from the instructions that cleared it.

Jaguar and Puma

Vectors and floating point: Scalar instructions such as SQRTSS and CVTSI2SD keep the rest of their destination and so wait for its last write, unless the core knows that part to be zero: it follows registers whose upper bits an instruction cleared until something nonzero lands there.

Zen and Zen+

Vectors and floating point: Scalar instructions such as SQRTSS or cvtsi2sd keep the upper part of their destination, and so wait for its last write, unless the core knows that part to be zero.

Zen 2

Vectors and floating point: Scalar instructions such as SQRTSS or cvtsi2sd keep the upper part of their destination and so wait for its last write, except when the core knows that part is zero.

Zen 3

Vectors and floating point: Scalar instructions such as SQRTSS or cvtsi2sd keep the upper part of their destination and so wait for its last write, except when the core knows that part is zero.

Zen 4

Vectors and floating point: Scalar instructions such as SQRTSS or cvtsi2sd keep the upper part of their destination and so wait for its last write, except when the core knows that part is zero.

Forms

Every encoding of SQRTSS that Intel XED knows, one row per XED instruction form (iform). How to read the notation.

Instruction	Encoding	Requires
`SQRTSS xmm, m32` SQRTSS_XMMss_MEMss	`F3 0F 51 /r`	SSE
`SQRTSS xmm, xmm` SQRTSS_XMMss_XMMss	`F3 0F 51 /r`	SSE

Data flow

Where the elements of the sources go, element 0 on the right; results that depend on a control value are drawn for an example. How to read.

Scalar: only the low single is computed; the other singles come from xmm1.

Result single 0 is computed from single 0 of xmm2; singles 3 to 1 are those of xmm1. Result singles 3 to 0: a3, a2, a1, r0.

Operation

What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.

xmm1.f32[0] = sqrt(src2.f32[0])
# xmm1.d[1] to [3] keep their values
# bits 128 and up of the register are unchanged

Run on AMD Zen 5 (EPYC 9645): 2 cases.

Operands

What each form reads and writes, as Intel XED records it: the operands of its syntax, in order, and the implicit ones that the syntax does not name. How to read.

Operand	Kind	Action
`SQRTSS xmm, xmm/m32`
`xmm`	explicit	read, write
`xmm/m32`	explicit	read

Flags

None: XED records no flag that the forms test or change.

Exceptions

The exception class is XED's name for the set of exception conditions that a form follows. How to read.

All forms: SSE_TYPE_3

Attributes

What else XED records about the forms. How to read.

All forms: follows MXCSR

Intrinsics

The C intrinsics of Clang 23.1.2 that compile to SQRTSS, each with the form it compiles to and the Clang options it needs. The forms come from compiling every intrinsic and decoding the result with Intel XED; all intrinsics A–Z explains the method.

Intrinsic	Compiles to
`_mm_sqrt_ss` `__m128 _mm_sqrt_ss(__m128 __a)`	`SQRTSS xmm, xmm` Legacy -msse

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

CPUID requirements and processors of the XED ISA sets above. Alternatives are separated by “or”; processors follow XED’s chip model, whose AMD processors end with Zen 2, and the CPU data of this site for Zen 3 to Zen 6.

ISA set	CPUID	Processors
`SSE` SSE	SSE `CPUID.01H:EDX[25]` SSE	Every x86-64 processor in XED’s model and Zen 3 to Zen 6

More SSE instructions

All 65 SSE instructions

sqrtf in compiled code#

The merge#